// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Tracing implementation internals
#include "verilated_vcd_c.h"
#include "VSimTop__Syms.h"


//======================

void VSimTop::trace(VerilatedVcdC* tfp, int, int) {
    tfp->spTrace()->addInitCb(&traceInit, __VlSymsp);
    traceRegister(tfp->spTrace());
}

void VSimTop::traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) {
    // Callback from tracep->open()
    VSimTop__Syms* __restrict vlSymsp = static_cast<VSimTop__Syms*>(userp);
    if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {
        VL_FATAL_MT(__FILE__, __LINE__, __FILE__,
                        "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.");
    }
    vlSymsp->__Vm_baseCode = code;
    tracep->module(vlSymsp->name());
    tracep->scopeEscape(' ');
    VSimTop::traceInitTop(vlSymsp, tracep);
    tracep->scopeEscape('.');
}

//======================


void VSimTop::traceInitTop(void* userp, VerilatedVcd* tracep) {
    VSimTop__Syms* __restrict vlSymsp = static_cast<VSimTop__Syms*>(userp);
    VSimTop* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    {
        vlTOPp->traceInitSub0(userp, tracep);
    }
}

void VSimTop::traceInitSub0(void* userp, VerilatedVcd* tracep) {
    VSimTop__Syms* __restrict vlSymsp = static_cast<VSimTop__Syms*>(userp);
    VSimTop* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    const int c = vlSymsp->__Vm_baseCode;
    if (false && tracep && c) {}  // Prevent unused
    // Body
    {
        tracep->declBit(c+799,"clock", false,-1);
        tracep->declBit(c+800,"reset", false,-1);
        tracep->declQuad(c+801,"io_logCtrl_log_begin", false,-1, 63,0);
        tracep->declQuad(c+803,"io_logCtrl_log_end", false,-1, 63,0);
        tracep->declQuad(c+805,"io_logCtrl_log_level", false,-1, 63,0);
        tracep->declBit(c+807,"io_perfInfo_clean", false,-1);
        tracep->declBit(c+808,"io_perfInfo_dump", false,-1);
        tracep->declBit(c+809,"io_uart_out_valid", false,-1);
        tracep->declBus(c+810,"io_uart_out_ch", false,-1, 7,0);
        tracep->declBit(c+811,"io_uart_in_valid", false,-1);
        tracep->declBus(c+812,"io_uart_in_ch", false,-1, 7,0);
        tracep->declBit(c+813,"io_memAXI_0_aw_ready", false,-1);
        tracep->declBit(c+814,"io_memAXI_0_aw_valid", false,-1);
        tracep->declQuad(c+815,"io_memAXI_0_aw_bits_addr", false,-1, 63,0);
        tracep->declBus(c+817,"io_memAXI_0_aw_bits_prot", false,-1, 2,0);
        tracep->declBus(c+818,"io_memAXI_0_aw_bits_id", false,-1, 3,0);
        tracep->declBus(c+819,"io_memAXI_0_aw_bits_user", false,-1, 0,0);
        tracep->declBus(c+820,"io_memAXI_0_aw_bits_len", false,-1, 7,0);
        tracep->declBus(c+821,"io_memAXI_0_aw_bits_size", false,-1, 2,0);
        tracep->declBus(c+822,"io_memAXI_0_aw_bits_burst", false,-1, 1,0);
        tracep->declBit(c+823,"io_memAXI_0_aw_bits_lock", false,-1);
        tracep->declBus(c+824,"io_memAXI_0_aw_bits_cache", false,-1, 3,0);
        tracep->declBus(c+825,"io_memAXI_0_aw_bits_qos", false,-1, 3,0);
        tracep->declBit(c+826,"io_memAXI_0_w_ready", false,-1);
        tracep->declBit(c+827,"io_memAXI_0_w_valid", false,-1);
        {int i; for (i=0; i<4; i++) {
                tracep->declQuad(c+828+i*2,"io_memAXI_0_w_bits_data", true,(i+0), 63,0);}}
        tracep->declBus(c+836,"io_memAXI_0_w_bits_strb", false,-1, 7,0);
        tracep->declBit(c+837,"io_memAXI_0_w_bits_last", false,-1);
        tracep->declBit(c+838,"io_memAXI_0_b_ready", false,-1);
        tracep->declBit(c+839,"io_memAXI_0_b_valid", false,-1);
        tracep->declBus(c+840,"io_memAXI_0_b_bits_resp", false,-1, 1,0);
        tracep->declBus(c+841,"io_memAXI_0_b_bits_id", false,-1, 3,0);
        tracep->declBus(c+842,"io_memAXI_0_b_bits_user", false,-1, 0,0);
        tracep->declBit(c+843,"io_memAXI_0_ar_ready", false,-1);
        tracep->declBit(c+844,"io_memAXI_0_ar_valid", false,-1);
        tracep->declQuad(c+845,"io_memAXI_0_ar_bits_addr", false,-1, 63,0);
        tracep->declBus(c+847,"io_memAXI_0_ar_bits_prot", false,-1, 2,0);
        tracep->declBus(c+848,"io_memAXI_0_ar_bits_id", false,-1, 3,0);
        tracep->declBus(c+849,"io_memAXI_0_ar_bits_user", false,-1, 0,0);
        tracep->declBus(c+850,"io_memAXI_0_ar_bits_len", false,-1, 7,0);
        tracep->declBus(c+851,"io_memAXI_0_ar_bits_size", false,-1, 2,0);
        tracep->declBus(c+852,"io_memAXI_0_ar_bits_burst", false,-1, 1,0);
        tracep->declBit(c+853,"io_memAXI_0_ar_bits_lock", false,-1);
        tracep->declBus(c+854,"io_memAXI_0_ar_bits_cache", false,-1, 3,0);
        tracep->declBus(c+855,"io_memAXI_0_ar_bits_qos", false,-1, 3,0);
        tracep->declBit(c+856,"io_memAXI_0_r_ready", false,-1);
        tracep->declBit(c+857,"io_memAXI_0_r_valid", false,-1);
        tracep->declBus(c+858,"io_memAXI_0_r_bits_resp", false,-1, 1,0);
        {int i; for (i=0; i<4; i++) {
                tracep->declQuad(c+859+i*2,"io_memAXI_0_r_bits_data", true,(i+0), 63,0);}}
        tracep->declBit(c+867,"io_memAXI_0_r_bits_last", false,-1);
        tracep->declBus(c+868,"io_memAXI_0_r_bits_id", false,-1, 3,0);
        tracep->declBus(c+869,"io_memAXI_0_r_bits_user", false,-1, 0,0);
        tracep->declBit(c+799,"SimTop clock", false,-1);
        tracep->declBit(c+800,"SimTop reset", false,-1);
        tracep->declQuad(c+801,"SimTop io_logCtrl_log_begin", false,-1, 63,0);
        tracep->declQuad(c+803,"SimTop io_logCtrl_log_end", false,-1, 63,0);
        tracep->declQuad(c+805,"SimTop io_logCtrl_log_level", false,-1, 63,0);
        tracep->declBit(c+807,"SimTop io_perfInfo_clean", false,-1);
        tracep->declBit(c+808,"SimTop io_perfInfo_dump", false,-1);
        tracep->declBit(c+809,"SimTop io_uart_out_valid", false,-1);
        tracep->declBus(c+810,"SimTop io_uart_out_ch", false,-1, 7,0);
        tracep->declBit(c+811,"SimTop io_uart_in_valid", false,-1);
        tracep->declBus(c+812,"SimTop io_uart_in_ch", false,-1, 7,0);
        tracep->declBit(c+813,"SimTop io_memAXI_0_aw_ready", false,-1);
        tracep->declBit(c+814,"SimTop io_memAXI_0_aw_valid", false,-1);
        tracep->declQuad(c+815,"SimTop io_memAXI_0_aw_bits_addr", false,-1, 63,0);
        tracep->declBus(c+817,"SimTop io_memAXI_0_aw_bits_prot", false,-1, 2,0);
        tracep->declBus(c+818,"SimTop io_memAXI_0_aw_bits_id", false,-1, 3,0);
        tracep->declBus(c+819,"SimTop io_memAXI_0_aw_bits_user", false,-1, 0,0);
        tracep->declBus(c+820,"SimTop io_memAXI_0_aw_bits_len", false,-1, 7,0);
        tracep->declBus(c+821,"SimTop io_memAXI_0_aw_bits_size", false,-1, 2,0);
        tracep->declBus(c+822,"SimTop io_memAXI_0_aw_bits_burst", false,-1, 1,0);
        tracep->declBit(c+823,"SimTop io_memAXI_0_aw_bits_lock", false,-1);
        tracep->declBus(c+824,"SimTop io_memAXI_0_aw_bits_cache", false,-1, 3,0);
        tracep->declBus(c+825,"SimTop io_memAXI_0_aw_bits_qos", false,-1, 3,0);
        tracep->declBit(c+826,"SimTop io_memAXI_0_w_ready", false,-1);
        tracep->declBit(c+827,"SimTop io_memAXI_0_w_valid", false,-1);
        {int i; for (i=0; i<4; i++) {
                tracep->declQuad(c+828+i*2,"SimTop io_memAXI_0_w_bits_data", true,(i+0), 63,0);}}
        tracep->declBus(c+836,"SimTop io_memAXI_0_w_bits_strb", false,-1, 7,0);
        tracep->declBit(c+837,"SimTop io_memAXI_0_w_bits_last", false,-1);
        tracep->declBit(c+838,"SimTop io_memAXI_0_b_ready", false,-1);
        tracep->declBit(c+839,"SimTop io_memAXI_0_b_valid", false,-1);
        tracep->declBus(c+840,"SimTop io_memAXI_0_b_bits_resp", false,-1, 1,0);
        tracep->declBus(c+841,"SimTop io_memAXI_0_b_bits_id", false,-1, 3,0);
        tracep->declBus(c+842,"SimTop io_memAXI_0_b_bits_user", false,-1, 0,0);
        tracep->declBit(c+843,"SimTop io_memAXI_0_ar_ready", false,-1);
        tracep->declBit(c+844,"SimTop io_memAXI_0_ar_valid", false,-1);
        tracep->declQuad(c+845,"SimTop io_memAXI_0_ar_bits_addr", false,-1, 63,0);
        tracep->declBus(c+847,"SimTop io_memAXI_0_ar_bits_prot", false,-1, 2,0);
        tracep->declBus(c+848,"SimTop io_memAXI_0_ar_bits_id", false,-1, 3,0);
        tracep->declBus(c+849,"SimTop io_memAXI_0_ar_bits_user", false,-1, 0,0);
        tracep->declBus(c+850,"SimTop io_memAXI_0_ar_bits_len", false,-1, 7,0);
        tracep->declBus(c+851,"SimTop io_memAXI_0_ar_bits_size", false,-1, 2,0);
        tracep->declBus(c+852,"SimTop io_memAXI_0_ar_bits_burst", false,-1, 1,0);
        tracep->declBit(c+853,"SimTop io_memAXI_0_ar_bits_lock", false,-1);
        tracep->declBus(c+854,"SimTop io_memAXI_0_ar_bits_cache", false,-1, 3,0);
        tracep->declBus(c+855,"SimTop io_memAXI_0_ar_bits_qos", false,-1, 3,0);
        tracep->declBit(c+856,"SimTop io_memAXI_0_r_ready", false,-1);
        tracep->declBit(c+857,"SimTop io_memAXI_0_r_valid", false,-1);
        tracep->declBus(c+858,"SimTop io_memAXI_0_r_bits_resp", false,-1, 1,0);
        {int i; for (i=0; i<4; i++) {
                tracep->declQuad(c+859+i*2,"SimTop io_memAXI_0_r_bits_data", true,(i+0), 63,0);}}
        tracep->declBit(c+867,"SimTop io_memAXI_0_r_bits_last", false,-1);
        tracep->declBus(c+868,"SimTop io_memAXI_0_r_bits_id", false,-1, 3,0);
        tracep->declBus(c+869,"SimTop io_memAXI_0_r_bits_user", false,-1, 0,0);
        tracep->declBit(c+813,"SimTop aw_ready", false,-1);
        tracep->declBit(c+87,"SimTop aw_valid", false,-1);
        tracep->declQuad(c+88,"SimTop aw_addr", false,-1, 63,0);
        tracep->declBus(c+888,"SimTop aw_prot", false,-1, 2,0);
        tracep->declBus(c+889,"SimTop aw_id", false,-1, 3,0);
        tracep->declBus(c+890,"SimTop aw_user", false,-1, 0,0);
        tracep->declBus(c+7,"SimTop aw_len", false,-1, 7,0);
        tracep->declBus(c+891,"SimTop aw_size", false,-1, 2,0);
        tracep->declBus(c+892,"SimTop aw_burst", false,-1, 1,0);
        tracep->declBit(c+893,"SimTop aw_lock", false,-1);
        tracep->declBus(c+894,"SimTop aw_cache", false,-1, 3,0);
        tracep->declBus(c+895,"SimTop aw_qos", false,-1, 3,0);
        tracep->declBus(c+896,"SimTop aw_region", false,-1, 3,0);
        tracep->declBit(c+826,"SimTop w_ready", false,-1);
        tracep->declBit(c+90,"SimTop w_valid", false,-1);
        tracep->declQuad(c+91,"SimTop w_data", false,-1, 63,0);
        tracep->declBus(c+93,"SimTop w_strb", false,-1, 7,0);
        tracep->declBit(c+897,"SimTop w_last", false,-1);
        tracep->declBus(c+898,"SimTop w_user", false,-1, 0,0);
        tracep->declBit(c+94,"SimTop b_ready", false,-1);
        tracep->declBit(c+839,"SimTop b_valid", false,-1);
        tracep->declBus(c+840,"SimTop b_resp", false,-1, 1,0);
        tracep->declBus(c+841,"SimTop b_id", false,-1, 3,0);
        tracep->declBus(c+842,"SimTop b_user", false,-1, 0,0);
        tracep->declBit(c+843,"SimTop ar_ready", false,-1);
        tracep->declBit(c+8,"SimTop ar_valid", false,-1);
        tracep->declQuad(c+9,"SimTop ar_addr", false,-1, 63,0);
        tracep->declBus(c+899,"SimTop ar_prot", false,-1, 2,0);
        tracep->declBus(c+870,"SimTop ar_id", false,-1, 3,0);
        tracep->declBus(c+900,"SimTop ar_user", false,-1, 0,0);
        tracep->declBus(c+7,"SimTop ar_len", false,-1, 7,0);
        tracep->declBus(c+891,"SimTop ar_size", false,-1, 2,0);
        tracep->declBus(c+892,"SimTop ar_burst", false,-1, 1,0);
        tracep->declBit(c+901,"SimTop ar_lock", false,-1);
        tracep->declBus(c+902,"SimTop ar_cache", false,-1, 3,0);
        tracep->declBus(c+903,"SimTop ar_qos", false,-1, 3,0);
        tracep->declBus(c+904,"SimTop ar_region", false,-1, 3,0);
        tracep->declBit(c+95,"SimTop r_ready", false,-1);
        tracep->declBit(c+857,"SimTop r_valid", false,-1);
        tracep->declBus(c+858,"SimTop r_resp", false,-1, 1,0);
        tracep->declQuad(c+871,"SimTop r_data", false,-1, 63,0);
        tracep->declBit(c+867,"SimTop r_last", false,-1);
        tracep->declBus(c+868,"SimTop r_id", false,-1, 3,0);
        tracep->declBus(c+869,"SimTop r_user", false,-1, 0,0);
        tracep->declBit(c+11,"SimTop r_hs", false,-1);
        tracep->declBit(c+12,"SimTop b_hs", false,-1);
        tracep->declBit(c+96,"SimTop mem_read", false,-1);
        tracep->declBus(c+97,"SimTop exe_s1", false,-1, 2,0);
        tracep->declBit(c+98,"SimTop mem_fetched", false,-1);
        tracep->declBit(c+99,"SimTop w_req_i", false,-1);
        tracep->declBit(c+905,"SimTop r_req_i", false,-1);
        tracep->declQuad(c+100,"SimTop if_addr", false,-1, 63,0);
        tracep->declBus(c+102,"SimTop if_inst", false,-1, 31,0);
        tracep->declBit(c+103,"SimTop axi_read_ready", false,-1);
        tracep->declBit(c+906,"SimTop axi_write_ready", false,-1);
        tracep->declQuad(c+104,"SimTop axi_data_read", false,-1, 63,0);
        tracep->declBus(c+106,"SimTop axi_resp", false,-1, 1,0);
        tracep->declBit(c+13,"SimTop axi_read_valid", false,-1);
        tracep->declQuad(c+14,"SimTop axi_read_addr", false,-1, 63,0);
        tracep->declBus(c+1,"SimTop axi_size", false,-1, 1,0);
        tracep->declQuad(c+107,"SimTop axi_write_data", false,-1, 63,0);
        tracep->declQuad(c+109,"SimTop axi_write_addr", false,-1, 63,0);
        tracep->declBus(c+93,"SimTop axi_write_mask", false,-1, 7,0);
        tracep->declBus(c+111,"SimTop axi_r_id_o", false,-1, 3,0);
        tracep->declBus(c+841,"SimTop axi_b_id_o", false,-1, 3,0);
        tracep->declBus(c+870,"SimTop axi_id", false,-1, 3,0);
        tracep->declQuad(c+112,"SimTop mem_read_data", false,-1, 63,0);
        tracep->declBit(c+114,"SimTop axi_mem_write", false,-1);
        tracep->declBit(c+99,"SimTop mem_write", false,-1);
        tracep->declBit(c+115,"SimTop axi_r_hs_o", false,-1);
        tracep->declQuad(c+873,"SimTop mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop mtime_open", false,-1);
        tracep->declBit(c+116,"SimTop clint_skip", false,-1);
        tracep->declBus(c+907,"SimTop ysyx_210448_u_axi_rw RW_DATA_WIDTH", false,-1, 31,0);
        tracep->declBus(c+907,"SimTop ysyx_210448_u_axi_rw RW_ADDR_WIDTH", false,-1, 31,0);
        tracep->declBus(c+907,"SimTop ysyx_210448_u_axi_rw AXI_DATA_WIDTH", false,-1, 31,0);
        tracep->declBus(c+907,"SimTop ysyx_210448_u_axi_rw AXI_ADDR_WIDTH", false,-1, 31,0);
        tracep->declBus(c+908,"SimTop ysyx_210448_u_axi_rw AXI_ID_WIDTH", false,-1, 31,0);
        tracep->declBus(c+909,"SimTop ysyx_210448_u_axi_rw AXI_USER_WIDTH", false,-1, 31,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_axi_rw clock", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_axi_rw reset", false,-1);
        tracep->declBus(c+870,"SimTop ysyx_210448_u_axi_rw axi_read_id", false,-1, 3,0);
        tracep->declBit(c+13,"SimTop ysyx_210448_u_axi_rw rw_valid_i", false,-1);
        tracep->declQuad(c+107,"SimTop ysyx_210448_u_axi_rw data_write_i", false,-1, 63,0);
        tracep->declQuad(c+14,"SimTop ysyx_210448_u_axi_rw rw_addr_i", false,-1, 63,0);
        tracep->declBit(c+905,"SimTop ysyx_210448_u_axi_rw r_req_i", false,-1);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_axi_rw w_req_i", false,-1);
        tracep->declBus(c+1,"SimTop ysyx_210448_u_axi_rw rw_size_i", false,-1, 1,0);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_axi_rw rw_ready_o", false,-1);
        tracep->declQuad(c+104,"SimTop ysyx_210448_u_axi_rw data_read_o", false,-1, 63,0);
        tracep->declBus(c+106,"SimTop ysyx_210448_u_axi_rw rw_resp_o", false,-1, 1,0);
        tracep->declBit(c+114,"SimTop ysyx_210448_u_axi_rw axi_write_valid", false,-1);
        tracep->declBus(c+93,"SimTop ysyx_210448_u_axi_rw w_mem_mask", false,-1, 7,0);
        tracep->declQuad(c+109,"SimTop ysyx_210448_u_axi_rw w_mem_addr", false,-1, 63,0);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_axi_rw mem_write", false,-1);
        tracep->declBus(c+97,"SimTop ysyx_210448_u_axi_rw exe_s1", false,-1, 2,0);
        tracep->declQuad(c+873,"SimTop ysyx_210448_u_axi_rw mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop ysyx_210448_u_axi_rw mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop ysyx_210448_u_axi_rw mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop ysyx_210448_u_axi_rw mtime_open", false,-1);
        tracep->declBit(c+116,"SimTop ysyx_210448_u_axi_rw clint_skip", false,-1);
        tracep->declBit(c+813,"SimTop ysyx_210448_u_axi_rw axi_aw_ready_i", false,-1);
        tracep->declBit(c+87,"SimTop ysyx_210448_u_axi_rw axi_aw_valid_o", false,-1);
        tracep->declQuad(c+88,"SimTop ysyx_210448_u_axi_rw axi_aw_addr_o", false,-1, 63,0);
        tracep->declBus(c+889,"SimTop ysyx_210448_u_axi_rw axi_aw_id_o", false,-1, 3,0);
        tracep->declBus(c+7,"SimTop ysyx_210448_u_axi_rw axi_aw_len_o", false,-1, 7,0);
        tracep->declBus(c+891,"SimTop ysyx_210448_u_axi_rw axi_aw_size_o", false,-1, 2,0);
        tracep->declBus(c+892,"SimTop ysyx_210448_u_axi_rw axi_aw_burst_o", false,-1, 1,0);
        tracep->declBit(c+826,"SimTop ysyx_210448_u_axi_rw axi_w_ready_i", false,-1);
        tracep->declBit(c+90,"SimTop ysyx_210448_u_axi_rw axi_w_valid_o", false,-1);
        tracep->declQuad(c+91,"SimTop ysyx_210448_u_axi_rw axi_w_data_o", false,-1, 63,0);
        tracep->declBus(c+93,"SimTop ysyx_210448_u_axi_rw axi_w_strb_o", false,-1, 7,0);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_axi_rw axi_w_last_o", false,-1);
        tracep->declBit(c+94,"SimTop ysyx_210448_u_axi_rw axi_b_ready_o", false,-1);
        tracep->declBit(c+839,"SimTop ysyx_210448_u_axi_rw axi_b_valid_i", false,-1);
        tracep->declBus(c+840,"SimTop ysyx_210448_u_axi_rw axi_b_resp_i", false,-1, 1,0);
        tracep->declBus(c+841,"SimTop ysyx_210448_u_axi_rw axi_b_id_i", false,-1, 3,0);
        tracep->declBus(c+841,"SimTop ysyx_210448_u_axi_rw axi_b_id_o", false,-1, 3,0);
        tracep->declBit(c+843,"SimTop ysyx_210448_u_axi_rw axi_ar_ready_i", false,-1);
        tracep->declBit(c+8,"SimTop ysyx_210448_u_axi_rw axi_ar_valid_o", false,-1);
        tracep->declQuad(c+9,"SimTop ysyx_210448_u_axi_rw axi_ar_addr_o", false,-1, 63,0);
        tracep->declBus(c+870,"SimTop ysyx_210448_u_axi_rw axi_ar_id_o", false,-1, 3,0);
        tracep->declBus(c+7,"SimTop ysyx_210448_u_axi_rw axi_ar_len_o", false,-1, 7,0);
        tracep->declBus(c+891,"SimTop ysyx_210448_u_axi_rw axi_ar_size_o", false,-1, 2,0);
        tracep->declBus(c+892,"SimTop ysyx_210448_u_axi_rw axi_ar_burst_o", false,-1, 1,0);
        tracep->declBit(c+95,"SimTop ysyx_210448_u_axi_rw axi_r_ready_o", false,-1);
        tracep->declBit(c+857,"SimTop ysyx_210448_u_axi_rw axi_r_valid_i", false,-1);
        tracep->declBus(c+858,"SimTop ysyx_210448_u_axi_rw axi_r_resp_i", false,-1, 1,0);
        tracep->declQuad(c+871,"SimTop ysyx_210448_u_axi_rw axi_r_data_i", false,-1, 63,0);
        tracep->declBit(c+867,"SimTop ysyx_210448_u_axi_rw axi_r_last_i", false,-1);
        tracep->declBus(c+868,"SimTop ysyx_210448_u_axi_rw axi_r_id_i", false,-1, 3,0);
        tracep->declBus(c+111,"SimTop ysyx_210448_u_axi_rw axi_r_id_o", false,-1, 3,0);
        tracep->declQuad(c+112,"SimTop ysyx_210448_u_axi_rw mem_data_read", false,-1, 63,0);
        tracep->declBit(c+11,"SimTop ysyx_210448_u_axi_rw r_hs", false,-1);
        tracep->declBit(c+12,"SimTop ysyx_210448_u_axi_rw b_hs", false,-1);
        tracep->declBit(c+115,"SimTop ysyx_210448_u_axi_rw axi_r_hs_o", false,-1);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_axi_rw w_trans", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_axi_rw r_trans", false,-1);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_axi_rw w_valid", false,-1);
        tracep->declBit(c+13,"SimTop ysyx_210448_u_axi_rw r_valid", false,-1);
        tracep->declBit(c+18,"SimTop ysyx_210448_u_axi_rw aw_hs", false,-1);
        tracep->declBit(c+19,"SimTop ysyx_210448_u_axi_rw w_hs", false,-1);
        tracep->declBit(c+20,"SimTop ysyx_210448_u_axi_rw ar_hs", false,-1);
        tracep->declBit(c+19,"SimTop ysyx_210448_u_axi_rw w_done", false,-1);
        tracep->declBit(c+21,"SimTop ysyx_210448_u_axi_rw r_done", false,-1);
        tracep->declBit(c+21,"SimTop ysyx_210448_u_axi_rw trans_done", false,-1);
        tracep->declBus(c+910,"SimTop ysyx_210448_u_axi_rw W_STATE_IDLE", false,-1, 1,0);
        tracep->declBus(c+892,"SimTop ysyx_210448_u_axi_rw W_STATE_ADDR", false,-1, 1,0);
        tracep->declBus(c+911,"SimTop ysyx_210448_u_axi_rw W_STATE_WRITE", false,-1, 1,0);
        tracep->declBus(c+912,"SimTop ysyx_210448_u_axi_rw W_STATE_RESP", false,-1, 1,0);
        tracep->declBus(c+910,"SimTop ysyx_210448_u_axi_rw R_STATE_IDLE", false,-1, 1,0);
        tracep->declBus(c+892,"SimTop ysyx_210448_u_axi_rw R_STATE_ADDR", false,-1, 1,0);
        tracep->declBus(c+911,"SimTop ysyx_210448_u_axi_rw R_STATE_READ", false,-1, 1,0);
        tracep->declBus(c+117,"SimTop ysyx_210448_u_axi_rw w_state", false,-1, 1,0);
        tracep->declBus(c+118,"SimTop ysyx_210448_u_axi_rw r_state", false,-1, 1,0);
        tracep->declBit(c+119,"SimTop ysyx_210448_u_axi_rw w_state_idle", false,-1);
        tracep->declBit(c+87,"SimTop ysyx_210448_u_axi_rw w_state_addr", false,-1);
        tracep->declBit(c+90,"SimTop ysyx_210448_u_axi_rw w_state_write", false,-1);
        tracep->declBit(c+94,"SimTop ysyx_210448_u_axi_rw w_state_resp", false,-1);
        tracep->declBit(c+120,"SimTop ysyx_210448_u_axi_rw r_state_idle", false,-1);
        tracep->declBit(c+121,"SimTop ysyx_210448_u_axi_rw r_state_addr", false,-1);
        tracep->declBit(c+95,"SimTop ysyx_210448_u_axi_rw r_state_read", false,-1);
        tracep->declBus(c+122,"SimTop ysyx_210448_u_axi_rw len", false,-1, 7,0);
        tracep->declBit(c+877,"SimTop ysyx_210448_u_axi_rw len_reset", false,-1);
        tracep->declBit(c+82,"SimTop ysyx_210448_u_axi_rw len_incr_en", false,-1);
        tracep->declBus(c+913,"SimTop ysyx_210448_u_axi_rw ALIGNED_WIDTH", false,-1, 31,0);
        tracep->declBus(c+914,"SimTop ysyx_210448_u_axi_rw OFFSET_WIDTH", false,-1, 31,0);
        tracep->declBus(c+913,"SimTop ysyx_210448_u_axi_rw AXI_SIZE", false,-1, 31,0);
        tracep->declBus(c+915,"SimTop ysyx_210448_u_axi_rw MASK_WIDTH", false,-1, 31,0);
        tracep->declBus(c+909,"SimTop ysyx_210448_u_axi_rw TRANS_LEN", false,-1, 31,0);
        tracep->declBus(c+916,"SimTop ysyx_210448_u_axi_rw BLOCK_TRANS", false,-1, 0,0);
        tracep->declBit(c+22,"SimTop ysyx_210448_u_axi_rw aligned", false,-1);
        tracep->declBit(c+2,"SimTop ysyx_210448_u_axi_rw size_b", false,-1);
        tracep->declBit(c+3,"SimTop ysyx_210448_u_axi_rw size_h", false,-1);
        tracep->declBit(c+4,"SimTop ysyx_210448_u_axi_rw size_w", false,-1);
        tracep->declBit(c+5,"SimTop ysyx_210448_u_axi_rw size_d", false,-1);
        tracep->declBus(c+23,"SimTop ysyx_210448_u_axi_rw addr_op1", false,-1, 3,0);
        tracep->declBus(c+6,"SimTop ysyx_210448_u_axi_rw addr_op2", false,-1, 3,0);
        tracep->declBus(c+24,"SimTop ysyx_210448_u_axi_rw addr_end", false,-1, 3,0);
        tracep->declBit(c+25,"SimTop ysyx_210448_u_axi_rw overstep", false,-1);
        tracep->declBus(c+7,"SimTop ysyx_210448_u_axi_rw axi_len", false,-1, 7,0);
        tracep->declBus(c+891,"SimTop ysyx_210448_u_axi_rw axi_size", false,-1, 2,0);
        tracep->declQuad(c+9,"SimTop ysyx_210448_u_axi_rw axi_addr", false,-1, 63,0);
        tracep->declBus(c+26,"SimTop ysyx_210448_u_axi_rw aligned_offset_l", false,-1, 5,0);
        tracep->declBus(c+27,"SimTop ysyx_210448_u_axi_rw aligned_offset_h", false,-1, 5,0);
        tracep->declArray(c+28,"SimTop ysyx_210448_u_axi_rw mask", false,-1, 127,0);
        tracep->declQuad(c+32,"SimTop ysyx_210448_u_axi_rw mask_l", false,-1, 63,0);
        tracep->declQuad(c+34,"SimTop ysyx_210448_u_axi_rw mask_h", false,-1, 63,0);
        tracep->declBus(c+870,"SimTop ysyx_210448_u_axi_rw axi_id", false,-1, 3,0);
        tracep->declBus(c+905,"SimTop ysyx_210448_u_axi_rw axi_user", false,-1, 0,0);
        tracep->declQuad(c+88,"SimTop ysyx_210448_u_axi_rw axi_write_addr", false,-1, 63,0);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_axi_rw rw_ready", false,-1);
        tracep->declBit(c+21,"SimTop ysyx_210448_u_axi_rw rw_ready_nxt", false,-1);
        tracep->declBit(c+83,"SimTop ysyx_210448_u_axi_rw rw_ready_en", false,-1);
        tracep->declBus(c+106,"SimTop ysyx_210448_u_axi_rw rw_resp", false,-1, 1,0);
        tracep->declBus(c+878,"SimTop ysyx_210448_u_axi_rw rw_resp_nxt", false,-1, 1,0);
        tracep->declBit(c+21,"SimTop ysyx_210448_u_axi_rw resp_en", false,-1);
        tracep->declBit(c+917,"SimTop ysyx_210448_u_axi_rw clint_skip_ready", false,-1);
        tracep->declQuad(c+36,"SimTop ysyx_210448_u_axi_rw axi_r_data_l", false,-1, 63,0);
        tracep->declQuad(c+879,"SimTop ysyx_210448_u_axi_rw axi_r_data_h", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu clock", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu reset", false,-1);
        tracep->declBus(c+111,"SimTop ysyx_210448_u_cpu axi_r_id_i", false,-1, 3,0);
        tracep->declBus(c+841,"SimTop ysyx_210448_u_cpu axi_b_id_i", false,-1, 3,0);
        tracep->declBus(c+868,"SimTop ysyx_210448_u_cpu axi_r_id", false,-1, 3,0);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu axi_read_ready", false,-1);
        tracep->declQuad(c+104,"SimTop ysyx_210448_u_cpu axi_data_read", false,-1, 63,0);
        tracep->declBus(c+106,"SimTop ysyx_210448_u_cpu axi_resp", false,-1, 1,0);
        tracep->declQuad(c+873,"SimTop ysyx_210448_u_cpu mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop ysyx_210448_u_cpu mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop ysyx_210448_u_cpu mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop ysyx_210448_u_cpu mtime_open", false,-1);
        tracep->declBit(c+116,"SimTop ysyx_210448_u_cpu clint_skip", false,-1);
        tracep->declBit(c+115,"SimTop ysyx_210448_u_cpu r_hs", false,-1);
        tracep->declBit(c+12,"SimTop ysyx_210448_u_cpu b_hs", false,-1);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu mem_fetched", false,-1);
        tracep->declBus(c+102,"SimTop ysyx_210448_u_cpu if_inst", false,-1, 31,0);
        tracep->declQuad(c+100,"SimTop ysyx_210448_u_cpu if_addr", false,-1, 63,0);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu mem_read", false,-1);
        tracep->declQuad(c+112,"SimTop ysyx_210448_u_cpu r_data", false,-1, 63,0);
        tracep->declBit(c+857,"SimTop ysyx_210448_u_cpu r_valid", false,-1);
        tracep->declBit(c+13,"SimTop ysyx_210448_u_cpu axi_read_valid", false,-1);
        tracep->declQuad(c+14,"SimTop ysyx_210448_u_cpu axi_read_addr", false,-1, 63,0);
        tracep->declBus(c+1,"SimTop ysyx_210448_u_cpu axi_size", false,-1, 1,0);
        tracep->declQuad(c+107,"SimTop ysyx_210448_u_cpu axi_write_data", false,-1, 63,0);
        tracep->declQuad(c+109,"SimTop ysyx_210448_u_cpu axi_write_addr", false,-1, 63,0);
        tracep->declBus(c+93,"SimTop ysyx_210448_u_cpu axi_write_mask", false,-1, 7,0);
        tracep->declBus(c+870,"SimTop ysyx_210448_u_cpu axi_id", false,-1, 3,0);
        tracep->declBit(c+114,"SimTop ysyx_210448_u_cpu axi_mem_write", false,-1);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_cpu mem_write", false,-1);
        tracep->declBus(c+97,"SimTop ysyx_210448_u_cpu exe_s1", false,-1, 2,0);
        tracep->declBit(c+809,"SimTop ysyx_210448_u_cpu io_uart_out_valid", false,-1);
        tracep->declBus(c+810,"SimTop ysyx_210448_u_cpu io_uart_out_ch", false,-1, 7,0);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu if_id_bubble", false,-1);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu id_exe_bubble", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu if_ar_hand", false,-1);
        tracep->declQuad(c+39,"SimTop ysyx_210448_u_cpu pc_add", false,-1, 63,0);
        tracep->declBit(c+41,"SimTop ysyx_210448_u_cpu pc_write", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu if_ar_valid", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu if_pc", false,-1, 63,0);
        tracep->declQuad(c+918,"SimTop ysyx_210448_u_cpu if_pc_if", false,-1, 63,0);
        tracep->declBus(c+920,"SimTop ysyx_210448_u_cpu if_inst_if", false,-1, 31,0);
        tracep->declBit(c+125,"SimTop ysyx_210448_u_cpu if_stop", false,-1);
        tracep->declBit(c+126,"SimTop ysyx_210448_u_cpu if_fetched", false,-1);
        tracep->declBit(c+84,"SimTop ysyx_210448_u_cpu handshake_done", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu if_id_en", false,-1);
        tracep->declBit(c+921,"SimTop ysyx_210448_u_cpu if_clk", false,-1);
        tracep->declQuad(c+127,"SimTop ysyx_210448_u_cpu id_pc", false,-1, 63,0);
        tracep->declBus(c+129,"SimTop ysyx_210448_u_cpu id_inst", false,-1, 31,0);
        tracep->declBus(c+130,"SimTop ysyx_210448_u_cpu id_rd", false,-1, 4,0);
        tracep->declBus(c+131,"SimTop ysyx_210448_u_cpu id_opcode", false,-1, 6,0);
        tracep->declBus(c+132,"SimTop ysyx_210448_u_cpu id_u_imm", false,-1, 19,0);
        tracep->declBus(c+133,"SimTop ysyx_210448_u_cpu id_j_imm", false,-1, 19,0);
        tracep->declBus(c+134,"SimTop ysyx_210448_u_cpu id_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+135,"SimTop ysyx_210448_u_cpu id_i_imm", false,-1, 11,0);
        tracep->declBus(c+136,"SimTop ysyx_210448_u_cpu id_I_imm", false,-1, 11,0);
        tracep->declBus(c+137,"SimTop ysyx_210448_u_cpu id_b_imm", false,-1, 6,0);
        tracep->declBus(c+138,"SimTop ysyx_210448_u_cpu id_s_imm", false,-1, 6,0);
        tracep->declBus(c+139,"SimTop ysyx_210448_u_cpu id_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+140,"SimTop ysyx_210448_u_cpu id_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+141,"SimTop ysyx_210448_u_cpu id_w_imm", false,-1, 11,0);
        tracep->declBus(c+142,"SimTop ysyx_210448_u_cpu id_w_shamt", false,-1, 5,0);
        tracep->declBus(c+143,"SimTop ysyx_210448_u_cpu id_s1", false,-1, 2,0);
        tracep->declBit(c+144,"SimTop ysyx_210448_u_cpu id_s2", false,-1);
        tracep->declBus(c+145,"SimTop ysyx_210448_u_cpu id_shamt", false,-1, 5,0);
        tracep->declBus(c+146,"SimTop ysyx_210448_u_cpu id_csr", false,-1, 11,0);
        tracep->declBus(c+147,"SimTop ysyx_210448_u_cpu id_zimm", false,-1, 4,0);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu id_csr_read", false,-1);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu id_csr_write", false,-1);
        tracep->declQuad(c+881,"SimTop ysyx_210448_u_cpu id_op1", false,-1, 63,0);
        tracep->declQuad(c+883,"SimTop ysyx_210448_u_cpu id_op2", false,-1, 63,0);
        tracep->declBit(c+149,"SimTop ysyx_210448_u_cpu id_ena1", false,-1);
        tracep->declBit(c+150,"SimTop ysyx_210448_u_cpu id_ena2", false,-1);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu id_rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu id_rs2", false,-1, 4,0);
        tracep->declQuad(c+885,"SimTop ysyx_210448_u_cpu id_t", false,-1, 63,0);
        tracep->declBit(c+922,"SimTop ysyx_210448_u_cpu id_open", false,-1);
        tracep->declBit(c+923,"SimTop ysyx_210448_u_cpu exe_open", false,-1);
        tracep->declBus(c+153,"SimTop ysyx_210448_u_cpu rs1", false,-1, 4,0);
        tracep->declBus(c+154,"SimTop ysyx_210448_u_cpu rs2", false,-1, 4,0);
        tracep->declQuad(c+924,"SimTop ysyx_210448_u_cpu id_pc_id", false,-1, 63,0);
        tracep->declBus(c+926,"SimTop ysyx_210448_u_cpu id_inst_id", false,-1, 31,0);
        tracep->declBus(c+927,"SimTop ysyx_210448_u_cpu id_opcode_id", false,-1, 6,0);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu id_exe_en", false,-1);
        tracep->declQuad(c+155,"SimTop ysyx_210448_u_cpu exe_pc", false,-1, 63,0);
        tracep->declBus(c+157,"SimTop ysyx_210448_u_cpu exe_inst", false,-1, 31,0);
        tracep->declQuad(c+158,"SimTop ysyx_210448_u_cpu exe_op1", false,-1, 63,0);
        tracep->declQuad(c+160,"SimTop ysyx_210448_u_cpu exe_op2", false,-1, 63,0);
        tracep->declBus(c+162,"SimTop ysyx_210448_u_cpu exe_rd", false,-1, 4,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu exe_opcode", false,-1, 6,0);
        tracep->declBus(c+164,"SimTop ysyx_210448_u_cpu exe_u_imm", false,-1, 19,0);
        tracep->declBus(c+165,"SimTop ysyx_210448_u_cpu exe_j_imm", false,-1, 19,0);
        tracep->declBus(c+166,"SimTop ysyx_210448_u_cpu exe_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+167,"SimTop ysyx_210448_u_cpu exe_i_imm", false,-1, 11,0);
        tracep->declBus(c+168,"SimTop ysyx_210448_u_cpu exe_I_imm", false,-1, 11,0);
        tracep->declBus(c+169,"SimTop ysyx_210448_u_cpu exe_b_imm", false,-1, 6,0);
        tracep->declBus(c+170,"SimTop ysyx_210448_u_cpu exe_s_imm", false,-1, 6,0);
        tracep->declBus(c+171,"SimTop ysyx_210448_u_cpu exe_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+172,"SimTop ysyx_210448_u_cpu exe_i_imm_i", false,-1, 4,0);
        tracep->declBus(c+173,"SimTop ysyx_210448_u_cpu exe_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+174,"SimTop ysyx_210448_u_cpu exe_w_imm", false,-1, 11,0);
        tracep->declBus(c+175,"SimTop ysyx_210448_u_cpu exe_w_shamt", false,-1, 5,0);
        tracep->declBit(c+176,"SimTop ysyx_210448_u_cpu exe_s2", false,-1);
        tracep->declBus(c+177,"SimTop ysyx_210448_u_cpu shamt", false,-1, 5,0);
        tracep->declBus(c+178,"SimTop ysyx_210448_u_cpu exe_csr", false,-1, 11,0);
        tracep->declBus(c+179,"SimTop ysyx_210448_u_cpu exe_zimm", false,-1, 4,0);
        tracep->declBit(c+180,"SimTop ysyx_210448_u_cpu exe_csr_read", false,-1);
        tracep->declBit(c+181,"SimTop ysyx_210448_u_cpu exe_csr_write", false,-1);
        tracep->declBit(c+42,"SimTop ysyx_210448_u_cpu exe_pc_write", false,-1);
        tracep->declQuad(c+182,"SimTop ysyx_210448_u_cpu exe_t", false,-1, 63,0);
        tracep->declQuad(c+43,"SimTop ysyx_210448_u_cpu exe_csr_data", false,-1, 63,0);
        tracep->declQuad(c+45,"SimTop ysyx_210448_u_cpu exe_data", false,-1, 63,0);
        tracep->declBit(c+184,"SimTop ysyx_210448_u_cpu exe_w_ena", false,-1);
        tracep->declBit(c+85,"SimTop ysyx_210448_u_cpu exe_skip", false,-1);
        tracep->declBit(c+185,"SimTop ysyx_210448_u_cpu mem_open", false,-1);
        tracep->declBit(c+47,"SimTop ysyx_210448_u_cpu exe_mem_en", false,-1);
        tracep->declQuad(c+186,"SimTop ysyx_210448_u_cpu mem_pc", false,-1, 63,0);
        tracep->declBus(c+188,"SimTop ysyx_210448_u_cpu mem_inst", false,-1, 31,0);
        tracep->declBus(c+189,"SimTop ysyx_210448_u_cpu mem_opcode", false,-1, 6,0);
        tracep->declBus(c+190,"SimTop ysyx_210448_u_cpu mem_s_imm", false,-1, 6,0);
        tracep->declBus(c+191,"SimTop ysyx_210448_u_cpu mem_s_imm_s", false,-1, 4,0);
        tracep->declQuad(c+192,"SimTop ysyx_210448_u_cpu mem_op1", false,-1, 63,0);
        tracep->declQuad(c+194,"SimTop ysyx_210448_u_cpu mem_op2", false,-1, 63,0);
        tracep->declBus(c+196,"SimTop ysyx_210448_u_cpu mem_I_imm", false,-1, 11,0);
        tracep->declBus(c+197,"SimTop ysyx_210448_u_cpu mem_s1", false,-1, 2,0);
        tracep->declQuad(c+198,"SimTop ysyx_210448_u_cpu mem_data", false,-1, 63,0);
        tracep->declBit(c+200,"SimTop ysyx_210448_u_cpu mem_w_ena", false,-1);
        tracep->declQuad(c+201,"SimTop ysyx_210448_u_cpu mem_csr_data", false,-1, 63,0);
        tracep->declBit(c+203,"SimTop ysyx_210448_u_cpu mem_csr_read", false,-1);
        tracep->declBit(c+204,"SimTop ysyx_210448_u_cpu mem_csr_write", false,-1);
        tracep->declBus(c+205,"SimTop ysyx_210448_u_cpu mem_csr", false,-1, 11,0);
        tracep->declBit(c+206,"SimTop ysyx_210448_u_cpu mem_skip", false,-1);
        tracep->declBit(c+928,"SimTop ysyx_210448_u_cpu mem_ok", false,-1);
        tracep->declQuad(c+207,"SimTop ysyx_210448_u_cpu mem_read_data", false,-1, 63,0);
        tracep->declBit(c+209,"SimTop ysyx_210448_u_cpu wb_skip", false,-1);
        tracep->declBit(c+210,"SimTop ysyx_210448_u_cpu wb_open", false,-1);
        tracep->declBus(c+211,"SimTop ysyx_210448_u_cpu mem_rd", false,-1, 4,0);
        tracep->declBit(c+212,"SimTop ysyx_210448_u_cpu mem_wb_en", false,-1);
        tracep->declQuad(c+213,"SimTop ysyx_210448_u_cpu wb_pc", false,-1, 63,0);
        tracep->declBus(c+215,"SimTop ysyx_210448_u_cpu wb_inst", false,-1, 31,0);
        tracep->declBit(c+216,"SimTop ysyx_210448_u_cpu wb_w_ena", false,-1);
        tracep->declBus(c+217,"SimTop ysyx_210448_u_cpu wb_rd", false,-1, 4,0);
        tracep->declQuad(c+218,"SimTop ysyx_210448_u_cpu wb_data", false,-1, 63,0);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu wb_read", false,-1);
        tracep->declQuad(c+221,"SimTop ysyx_210448_u_cpu wb_read_data", false,-1, 63,0);
        tracep->declBus(c+223,"SimTop ysyx_210448_u_cpu wb_csr", false,-1, 11,0);
        tracep->declBit(c+224,"SimTop ysyx_210448_u_cpu wb_csr_write", false,-1);
        tracep->declBit(c+225,"SimTop ysyx_210448_u_cpu wb_csr_read", false,-1);
        tracep->declQuad(c+226,"SimTop ysyx_210448_u_cpu wb_csr_data", false,-1, 63,0);
        tracep->declBus(c+228,"SimTop ysyx_210448_u_cpu wb_opcode", false,-1, 6,0);
        tracep->declBit(c+229,"SimTop ysyx_210448_u_cpu ena2", false,-1);
        tracep->declBit(c+929,"SimTop ysyx_210448_u_cpu csr_skip", false,-1);
        tracep->declBit(c+230,"SimTop ysyx_210448_u_cpu wb_ok", false,-1);
        tracep->declQuad(c+930,"SimTop ysyx_210448_u_cpu t", false,-1, 63,0);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+231+i*2,"SimTop ysyx_210448_u_cpu regs_o", true,(i+0), 63,0);}}
        tracep->declQuad(c+295,"SimTop ysyx_210448_u_cpu mstatus", false,-1, 63,0);
        tracep->declQuad(c+297,"SimTop ysyx_210448_u_cpu mepc", false,-1, 63,0);
        tracep->declQuad(c+299,"SimTop ysyx_210448_u_cpu mtvec", false,-1, 63,0);
        tracep->declQuad(c+301,"SimTop ysyx_210448_u_cpu mcause", false,-1, 63,0);
        tracep->declQuad(c+303,"SimTop ysyx_210448_u_cpu mip", false,-1, 63,0);
        tracep->declQuad(c+305,"SimTop ysyx_210448_u_cpu mie", false,-1, 63,0);
        tracep->declQuad(c+48,"SimTop ysyx_210448_u_cpu mcause_data", false,-1, 63,0);
        tracep->declQuad(c+932,"SimTop ysyx_210448_u_cpu mstatus_data", false,-1, 63,0);
        tracep->declQuad(c+307,"SimTop ysyx_210448_u_cpu rmstatus", false,-1, 63,0);
        tracep->declQuad(c+309,"SimTop ysyx_210448_u_cpu mcycle", false,-1, 63,0);
        tracep->declQuad(c+311,"SimTop ysyx_210448_u_cpu mscratch", false,-1, 63,0);
        tracep->declQuad(c+313,"SimTop ysyx_210448_u_cpu sstatus", false,-1, 63,0);
        tracep->declBit(c+50,"SimTop ysyx_210448_u_cpu id_csr_skip", false,-1);
        tracep->declBit(c+315,"SimTop ysyx_210448_u_cpu exe_csr_skip", false,-1);
        tracep->declBit(c+316,"SimTop ysyx_210448_u_cpu mem_csr_skip", false,-1);
        tracep->declBit(c+317,"SimTop ysyx_210448_u_cpu wb_csr_skip", false,-1);
        tracep->declBit(c+934,"SimTop ysyx_210448_u_cpu c_interrupt", false,-1);
        tracep->declQuad(c+51,"SimTop ysyx_210448_u_cpu exe_pc_add", false,-1, 63,0);
        tracep->declQuad(c+318,"SimTop ysyx_210448_u_cpu mhartid", false,-1, 63,0);
        tracep->declQuad(c+320,"SimTop ysyx_210448_u_cpu csr_pc_add", false,-1, 63,0);
        tracep->declBit(c+322,"SimTop ysyx_210448_u_cpu csr_pc_write", false,-1);
        tracep->declBit(c+323,"SimTop ysyx_210448_u_cpu id_fetched", false,-1);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu exe_fetched", false,-1);
        tracep->declBit(c+325,"SimTop ysyx_210448_u_cpu wb_fetched", false,-1);
        tracep->declQuad(c+326,"SimTop ysyx_210448_u_cpu mem_read_addr", false,-1, 63,0);
        tracep->declQuad(c+328,"SimTop ysyx_210448_u_cpu rdata", false,-1, 63,0);
        tracep->declQuad(c+330,"SimTop ysyx_210448_u_cpu if_data_read", false,-1, 63,0);
        tracep->declBus(c+935,"SimTop ysyx_210448_u_cpu if_read_id", false,-1, 3,0);
        tracep->declBus(c+936,"SimTop ysyx_210448_u_cpu mem_read_id", false,-1, 3,0);
        tracep->declBit(c+937,"SimTop ysyx_210448_u_cpu if_axi_stop", false,-1);
        tracep->declBit(c+332,"SimTop ysyx_210448_u_cpu axi_mem_read", false,-1);
        tracep->declBit(c+938,"SimTop ysyx_210448_u_cpu wb_mem_read", false,-1);
        tracep->declBit(c+333,"SimTop ysyx_210448_u_cpu mem_read_close", false,-1);
        tracep->declBit(c+334,"SimTop ysyx_210448_u_cpu wb_write", false,-1);
        tracep->declBit(c+939,"SimTop ysyx_210448_u_cpu l_double", false,-1);
        tracep->declBit(c+940,"SimTop ysyx_210448_u_cpu close", false,-1);
        tracep->declBit(c+335,"SimTop ysyx_210448_u_cpu wb_close", false,-1);
        tracep->declBit(c+336,"SimTop ysyx_210448_u_cpu if_mem_read", false,-1);
        tracep->declBit(c+337,"SimTop ysyx_210448_u_cpu id_mem_read", false,-1);
        tracep->declBit(c+338,"SimTop ysyx_210448_u_cpu exe_mem_read", false,-1);
        tracep->declBit(c+339,"SimTop ysyx_210448_u_cpu mem_mem_read", false,-1);
        tracep->declBit(c+340,"SimTop ysyx_210448_u_cpu ena1", false,-1);
        tracep->declBus(c+341,"SimTop ysyx_210448_u_cpu s3", false,-1, 2,0);
        tracep->declBit(c+342,"SimTop ysyx_210448_u_cpu wb_write_ready", false,-1);
        tracep->declBit(c+343,"SimTop ysyx_210448_u_cpu mem_write_ready", false,-1);
        tracep->declBit(c+941,"SimTop ysyx_210448_u_cpu mem_mem_write", false,-1);
        tracep->declBit(c+942,"SimTop ysyx_210448_u_cpu if_mem_write", false,-1);
        tracep->declBit(c+943,"SimTop ysyx_210448_u_cpu id_mem_write", false,-1);
        tracep->declBit(c+344,"SimTop ysyx_210448_u_cpu if_w_ena", false,-1);
        tracep->declBit(c+345,"SimTop ysyx_210448_u_cpu id_w_ena", false,-1);
        tracep->declBit(c+346,"SimTop ysyx_210448_u_cpu ld", false,-1);
        tracep->declBit(c+53,"SimTop ysyx_210448_u_cpu clock_interrupt", false,-1);
        tracep->declBit(c+630,"SimTop ysyx_210448_u_cpu cmt_wen", false,-1);
        tracep->declBus(c+631,"SimTop ysyx_210448_u_cpu cmt_wdest", false,-1, 7,0);
        tracep->declQuad(c+632,"SimTop ysyx_210448_u_cpu cmt_wdata", false,-1, 63,0);
        tracep->declQuad(c+634,"SimTop ysyx_210448_u_cpu cmt_pc", false,-1, 63,0);
        tracep->declBus(c+636,"SimTop ysyx_210448_u_cpu cmt_inst", false,-1, 31,0);
        tracep->declBit(c+637,"SimTop ysyx_210448_u_cpu cmt_valid", false,-1);
        tracep->declBit(c+638,"SimTop ysyx_210448_u_cpu trap", false,-1);
        tracep->declBus(c+639,"SimTop ysyx_210448_u_cpu trap_code", false,-1, 7,0);
        tracep->declQuad(c+640,"SimTop ysyx_210448_u_cpu cycleCnt", false,-1, 63,0);
        tracep->declQuad(c+642,"SimTop ysyx_210448_u_cpu instrCnt", false,-1, 63,0);
        tracep->declBit(c+644,"SimTop ysyx_210448_u_cpu skip", false,-1);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+645+i*2,"SimTop ysyx_210448_u_cpu regs_diff", true,(i+0), 63,0);}}
        tracep->declBus(c+709,"SimTop ysyx_210448_u_cpu intrNO", false,-1, 31,0);
        tracep->declBus(c+710,"SimTop ysyx_210448_u_cpu cause", false,-1, 31,0);
        tracep->declQuad(c+711,"SimTop ysyx_210448_u_cpu mtvec_diff", false,-1, 63,0);
        tracep->declQuad(c+713,"SimTop ysyx_210448_u_cpu mstatus_diff", false,-1, 63,0);
        tracep->declQuad(c+715,"SimTop ysyx_210448_u_cpu sstatus_diff", false,-1, 63,0);
        tracep->declQuad(c+717,"SimTop ysyx_210448_u_cpu mepc_diff", false,-1, 63,0);
        tracep->declQuad(c+719,"SimTop ysyx_210448_u_cpu mcause_diff", false,-1, 63,0);
        tracep->declQuad(c+721,"SimTop ysyx_210448_u_cpu mip_diff", false,-1, 63,0);
        tracep->declQuad(c+723,"SimTop ysyx_210448_u_cpu mie_diff", false,-1, 63,0);
        tracep->declQuad(c+725,"SimTop ysyx_210448_u_cpu mscratch_diff", false,-1, 63,0);
        tracep->declQuad(c+944,"SimTop ysyx_210448_u_cpu mcause_arch", false,-1, 63,0);
        tracep->declQuad(c+727,"SimTop ysyx_210448_u_cpu mhartid_diff", false,-1, 63,0);
        tracep->declQuad(c+729,"SimTop ysyx_210448_u_cpu rmstatus_diff", false,-1, 63,0);
        tracep->declQuad(c+297,"SimTop ysyx_210448_u_cpu interrupt_pc", false,-1, 63,0);
        tracep->declBit(c+347,"SimTop ysyx_210448_u_cpu interrupt_ready1", false,-1);
        tracep->declBit(c+348,"SimTop ysyx_210448_u_cpu interrupt_ready2", false,-1);
        tracep->declQuad(c+349,"SimTop ysyx_210448_u_cpu mepc_exe", false,-1, 63,0);
        tracep->declBit(c+351,"SimTop ysyx_210448_u_cpu interrupt", false,-1);
        tracep->declQuad(c+946,"SimTop ysyx_210448_u_cpu mstatus_diff_diff", false,-1, 63,0);
        tracep->declQuad(c+948,"SimTop ysyx_210448_u_cpu mret", false,-1, 63,0);
        tracep->declBit(c+352,"SimTop ysyx_210448_u_cpu csr", false,-1);
        tracep->declBit(c+353,"SimTop ysyx_210448_u_cpu ecall_valid", false,-1);
        tracep->declBit(c+86,"SimTop ysyx_210448_u_cpu clock_valid", false,-1);
        tracep->declBit(c+887,"SimTop ysyx_210448_u_cpu inst_valid", false,-1);
        tracep->declBit(c+731,"SimTop ysyx_210448_u_cpu mstatus_mie", false,-1);
        tracep->declBit(c+732,"SimTop ysyx_210448_u_cpu mstatus_mpie", false,-1);
        tracep->declBit(c+950,"SimTop ysyx_210448_u_cpu interrupt_mie", false,-1);
        tracep->declBus(c+733,"SimTop ysyx_210448_u_cpu mstatus_fs", false,-1, 1,0);
        tracep->declBus(c+912,"SimTop ysyx_210448_u_cpu mpp", false,-1, 1,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter rst", false,-1);
        tracep->declBit(c+42,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter exe_pc_write", false,-1);
        tracep->declQuad(c+51,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter exe_pc_add", false,-1, 63,0);
        tracep->declBit(c+322,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter csr_pc_write", false,-1);
        tracep->declQuad(c+320,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter csr_pc_add", false,-1, 63,0);
        tracep->declBus(c+102,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter if_inst", false,-1, 31,0);
        tracep->declBit(c+332,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_mem_read", false,-1);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_read", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter if_ar_valid", false,-1);
        tracep->declBus(c+935,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter if_read_id", false,-1, 3,0);
        tracep->declBus(c+936,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_read_id", false,-1, 3,0);
        tracep->declBus(c+111,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_r_id_i", false,-1, 3,0);
        tracep->declBus(c+868,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_r_id", false,-1, 3,0);
        tracep->declBit(c+115,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter r_hs", false,-1);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter wb_read", false,-1);
        tracep->declQuad(c+112,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter r_data", false,-1, 63,0);
        tracep->declQuad(c+100,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter if_addr", false,-1, 63,0);
        tracep->declQuad(c+326,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_read_addr", false,-1, 63,0);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_read_ready", false,-1);
        tracep->declQuad(c+104,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_data_read", false,-1, 63,0);
        tracep->declQuad(c+330,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter if_read_data", false,-1, 63,0);
        tracep->declQuad(c+328,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_read_data", false,-1, 63,0);
        tracep->declBit(c+13,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_read_valid", false,-1);
        tracep->declQuad(c+14,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_addr", false,-1, 63,0);
        tracep->declBus(c+1,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_size", false,-1, 1,0);
        tracep->declBit(c+84,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter handshake_done", false,-1);
        tracep->declBus(c+870,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter axi_id", false,-1, 3,0);
        tracep->declBit(c+125,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter stop", false,-1);
        tracep->declBit(c+41,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter pc_write", false,-1);
        tracep->declQuad(c+39,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter pc_add", false,-1, 63,0);
        tracep->declBit(c+212,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_wb_en", false,-1);
        tracep->declBit(c+333,"SimTop ysyx_210448_u_cpu ysyx_210448_cpu_abtiter mem_read_close", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage rst", false,-1);
        tracep->declBit(c+125,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage stop", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_ready", false,-1);
        tracep->declBit(c+115,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage r_hs", false,-1);
        tracep->declQuad(c+330,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_data_read", false,-1, 63,0);
        tracep->declQuad(c+39,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage pc_add", false,-1, 63,0);
        tracep->declBit(c+41,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage pc_write", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_pc", false,-1, 63,0);
        tracep->declBus(c+102,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_inst", false,-1, 31,0);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_id_en", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_valid", false,-1);
        tracep->declQuad(c+100,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_addr", false,-1, 63,0);
        tracep->declBus(c+1,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_size", false,-1, 1,0);
        tracep->declBit(c+126,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_fetched", false,-1);
        tracep->declBus(c+935,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_read_id", false,-1, 3,0);
        tracep->declBit(c+336,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_mem_read", false,-1);
        tracep->declBit(c+344,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_w_ena", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_ar_hand", false,-1);
        tracep->declBit(c+332,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage axi_mem_read", false,-1);
        tracep->declBit(c+114,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage axi_mem_write", false,-1);
        tracep->declQuad(c+951,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage addr", false,-1, 63,0);
        tracep->declQuad(c+54,"SimTop ysyx_210448_u_cpu ysyx_210448_if_stage if_inst_data", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID rst", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_id_en", false,-1);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_id_bubble", false,-1);
        tracep->declBit(c+336,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_mem_read", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_pc", false,-1, 63,0);
        tracep->declBus(c+102,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_inst", false,-1, 31,0);
        tracep->declBit(c+344,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_w_ena", false,-1);
        tracep->declBit(c+126,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID if_fetched", false,-1);
        tracep->declQuad(c+127,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID id_pc", false,-1, 63,0);
        tracep->declBit(c+337,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID id_mem_read", false,-1);
        tracep->declBus(c+129,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID id_inst", false,-1, 31,0);
        tracep->declBit(c+345,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID id_w_ena", false,-1);
        tracep->declBit(c+323,"SimTop ysyx_210448_u_cpu ysyx_210448_IF_ID id_fetched", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage rst", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage if_pc", false,-1, 63,0);
        tracep->declBus(c+129,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_inst", false,-1, 31,0);
        tracep->declBus(c+130,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_rd", false,-1, 4,0);
        tracep->declBus(c+131,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_opcode", false,-1, 6,0);
        tracep->declBus(c+132,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_u_imm", false,-1, 19,0);
        tracep->declBus(c+133,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_j_imm", false,-1, 19,0);
        tracep->declBus(c+134,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+135,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_i_imm", false,-1, 11,0);
        tracep->declBus(c+136,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_I_imm", false,-1, 11,0);
        tracep->declBus(c+137,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_b_imm", false,-1, 6,0);
        tracep->declBus(c+138,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_s_imm", false,-1, 6,0);
        tracep->declBus(c+139,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+140,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+141,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_w_imm", false,-1, 11,0);
        tracep->declBus(c+142,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_w_shamt", false,-1, 5,0);
        tracep->declBus(c+143,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_s1", false,-1, 2,0);
        tracep->declBit(c+144,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_s2", false,-1);
        tracep->declBus(c+145,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_shamt", false,-1, 5,0);
        tracep->declBus(c+146,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_csr", false,-1, 11,0);
        tracep->declBus(c+147,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_zimm", false,-1, 4,0);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_csr_read", false,-1);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_csr_write", false,-1);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_rs2", false,-1, 4,0);
        tracep->declBit(c+149,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_ena1", false,-1);
        tracep->declBit(c+150,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_ena2", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_id_stage id_exe_en", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause rst", false,-1);
        tracep->declBit(c+230,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause wb_ok", false,-1);
        tracep->declBit(c+323,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause id_fetched", false,-1);
        tracep->declBit(c+340,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause ena1", false,-1);
        tracep->declBit(c+229,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause ena2", false,-1);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+354+i*2,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause regs_o", true,(i+0), 63,0);}}
        tracep->declQuad(c+45,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause exe_data", false,-1, 63,0);
        tracep->declQuad(c+198,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause mem_data", false,-1, 63,0);
        tracep->declBus(c+189,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause mem_opcode", false,-1, 6,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause exe_opcode", false,-1, 6,0);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause id_rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause id_rs2", false,-1, 4,0);
        tracep->declBit(c+149,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause id_ena1", false,-1);
        tracep->declBit(c+150,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause id_ena2", false,-1);
        tracep->declBus(c+162,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause exe_rd", false,-1, 4,0);
        tracep->declBus(c+211,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause mem_rd", false,-1, 4,0);
        tracep->declQuad(c+158,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause exe_op1", false,-1, 63,0);
        tracep->declQuad(c+160,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause exe_op2", false,-1, 63,0);
        tracep->declBit(c+346,"SimTop ysyx_210448_u_cpu ysyx_210448_Pause ld", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE rst", false,-1);
        tracep->declBit(c+323,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_fetched", false,-1);
        tracep->declBit(c+897,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_exe_en", false,-1);
        tracep->declBit(c+337,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_mem_read", false,-1);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_exe_bubble", false,-1);
        tracep->declBit(c+50,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_csr_skip", false,-1);
        tracep->declBit(c+345,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_w_ena", false,-1);
        tracep->declQuad(c+127,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_pc", false,-1, 63,0);
        tracep->declBus(c+129,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_inst", false,-1, 31,0);
        tracep->declQuad(c+881,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_op1", false,-1, 63,0);
        tracep->declQuad(c+883,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_op2", false,-1, 63,0);
        tracep->declQuad(c+885,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_t", false,-1, 63,0);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_rs2", false,-1, 4,0);
        tracep->declBus(c+130,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_rd", false,-1, 4,0);
        tracep->declBus(c+131,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_opcode", false,-1, 6,0);
        tracep->declBus(c+132,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_u_imm", false,-1, 19,0);
        tracep->declBus(c+133,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_j_imm", false,-1, 19,0);
        tracep->declBus(c+134,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+135,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_i_imm", false,-1, 11,0);
        tracep->declBus(c+136,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_I_imm", false,-1, 11,0);
        tracep->declBus(c+137,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_b_imm", false,-1, 6,0);
        tracep->declBus(c+138,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_s_imm", false,-1, 6,0);
        tracep->declBus(c+139,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+140,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+141,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_w_imm", false,-1, 11,0);
        tracep->declBus(c+142,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_w_shamt", false,-1, 5,0);
        tracep->declBus(c+143,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_s1", false,-1, 2,0);
        tracep->declBit(c+144,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_s2", false,-1);
        tracep->declBus(c+145,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_shamt", false,-1, 5,0);
        tracep->declBus(c+146,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_csr", false,-1, 11,0);
        tracep->declBus(c+147,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_zimm", false,-1, 4,0);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_csr_read", false,-1);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE id_csr_write", false,-1);
        tracep->declQuad(c+155,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_pc", false,-1, 63,0);
        tracep->declBus(c+157,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_inst", false,-1, 31,0);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_fetched", false,-1);
        tracep->declBit(c+315,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_csr_skip", false,-1);
        tracep->declBit(c+338,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_mem_read", false,-1);
        tracep->declBit(c+184,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_w_ena", false,-1);
        tracep->declQuad(c+158,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_op1", false,-1, 63,0);
        tracep->declQuad(c+160,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_op2", false,-1, 63,0);
        tracep->declQuad(c+182,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_t", false,-1, 63,0);
        tracep->declBus(c+153,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE rs1", false,-1, 4,0);
        tracep->declBus(c+154,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE rs2", false,-1, 4,0);
        tracep->declBus(c+162,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_rd", false,-1, 4,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_opcode", false,-1, 6,0);
        tracep->declBus(c+164,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_u_imm", false,-1, 19,0);
        tracep->declBus(c+165,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_j_imm", false,-1, 19,0);
        tracep->declBus(c+166,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+167,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_i_imm", false,-1, 11,0);
        tracep->declBus(c+168,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_I_imm", false,-1, 11,0);
        tracep->declBus(c+169,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_b_imm", false,-1, 6,0);
        tracep->declBus(c+170,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_s_imm", false,-1, 6,0);
        tracep->declBus(c+171,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+172,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_i_imm_i", false,-1, 4,0);
        tracep->declBus(c+173,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+174,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_w_imm", false,-1, 11,0);
        tracep->declBus(c+175,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_w_shamt", false,-1, 5,0);
        tracep->declBus(c+97,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_s1", false,-1, 2,0);
        tracep->declBit(c+176,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_s2", false,-1);
        tracep->declBus(c+177,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_shamt", false,-1, 5,0);
        tracep->declBus(c+178,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_csr", false,-1, 11,0);
        tracep->declBus(c+179,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_zimm", false,-1, 4,0);
        tracep->declBit(c+180,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_csr_read", false,-1);
        tracep->declBit(c+181,"SimTop ysyx_210448_u_cpu ysyx_210448_ID_EXE exe_csr_write", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage rst", false,-1);
        tracep->declBit(c+338,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_mem_read", false,-1);
        tracep->declBit(c+339,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage mem_mem_read", false,-1);
        tracep->declBit(c+115,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage r_hs", false,-1);
        tracep->declBus(c+111,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage axi_r_id_i", false,-1, 3,0);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_fetched", false,-1);
        tracep->declQuad(c+158,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_op1", false,-1, 63,0);
        tracep->declQuad(c+160,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_op2", false,-1, 63,0);
        tracep->declBus(c+162,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_rd", false,-1, 4,0);
        tracep->declQuad(c+155,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_pc", false,-1, 63,0);
        tracep->declBus(c+157,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_inst", false,-1, 31,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_opcode", false,-1, 6,0);
        tracep->declBus(c+164,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_u_imm", false,-1, 19,0);
        tracep->declBus(c+165,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_j_imm", false,-1, 19,0);
        tracep->declBus(c+166,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_j_imm_j", false,-1, 11,0);
        tracep->declBus(c+167,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_i_imm", false,-1, 11,0);
        tracep->declBus(c+169,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_b_imm", false,-1, 6,0);
        tracep->declBus(c+170,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_s_imm", false,-1, 6,0);
        tracep->declBus(c+171,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_s_imm_s", false,-1, 4,0);
        tracep->declBus(c+172,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_i_imm_i", false,-1, 4,0);
        tracep->declBus(c+168,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_I_imm", false,-1, 11,0);
        tracep->declBus(c+174,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_w_imm", false,-1, 11,0);
        tracep->declBus(c+175,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_w_shamt", false,-1, 5,0);
        tracep->declBus(c+177,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage shamt", false,-1, 5,0);
        tracep->declBus(c+173,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_b_imm_b", false,-1, 4,0);
        tracep->declBus(c+97,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_s1", false,-1, 2,0);
        tracep->declBit(c+176,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_s2", false,-1);
        tracep->declQuad(c+182,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_t", false,-1, 63,0);
        tracep->declBus(c+179,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_zimm", false,-1, 4,0);
        tracep->declQuad(c+43,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_csr_data", false,-1, 63,0);
        tracep->declQuad(c+45,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_data", false,-1, 63,0);
        tracep->declBit(c+184,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_w_ena", false,-1);
        tracep->declBit(c+85,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_skip", false,-1);
        tracep->declBit(c+42,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_pc_write", false,-1);
        tracep->declQuad(c+51,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_pc_add", false,-1, 63,0);
        tracep->declBit(c+47,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_mem_en", false,-1);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage if_id_bubble", false,-1);
        tracep->declBit(c+38,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage id_exe_bubble", false,-1);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage mem_read", false,-1);
        tracep->declBus(c+341,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage s3", false,-1, 2,0);
        tracep->declBus(c+810,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage io_uart_out_ch", false,-1, 7,0);
        tracep->declBit(c+809,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage io_uart_out_valid", false,-1);
        tracep->declQuad(c+56,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_u_imm_u", false,-1, 63,0);
        tracep->declQuad(c+58,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_b_imm_b_b_b", false,-1, 63,0);
        tracep->declBus(c+60,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_b_imm_b_b", false,-1, 11,0);
        tracep->declBus(c+61,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage jal_imm", false,-1, 19,0);
        tracep->declBus(c+953,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage s_s", false,-1, 11,0);
        tracep->declBit(c+62,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm1", false,-1);
        tracep->declBus(c+63,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm2", false,-1, 7,0);
        tracep->declBit(c+64,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm3", false,-1);
        tracep->declBus(c+65,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm4", false,-1, 9,0);
        tracep->declBus(c+66,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm5", false,-1, 5,0);
        tracep->declBus(c+67,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage imm6", false,-1, 3,0);
        tracep->declBus(c+68,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sra_imm", false,-1, 5,0);
        tracep->declBus(c+69,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sra_imm_w", false,-1, 4,0);
        tracep->declBus(c+70,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sll_imm", false,-1, 4,0);
        tracep->declBus(c+71,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sll_imm_sll", false,-1, 5,0);
        tracep->declBus(c+72,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage srl_imm", false,-1, 5,0);
        tracep->declBus(c+73,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage srl_imm_w", false,-1, 4,0);
        tracep->declQuad(c+74,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sllw", false,-1, 63,0);
        tracep->declBus(c+76,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage srlw", false,-1, 31,0);
        tracep->declBus(c+77,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage sraw", false,-1, 31,0);
        tracep->declBus(c+78,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage printf", false,-1, 7,0);
        tracep->declQuad(c+79,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage csr_zimm", false,-1, 63,0);
        tracep->declQuad(c+954,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage mepc_reserve", false,-1, 63,0);
        tracep->declBit(c+418,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage mem_read_open", false,-1);
        tracep->declQuad(c+419,"SimTop ysyx_210448_u_cpu ysyx_210448_exe_stage exe_mem_read_addr", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM rst", false,-1);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_fetched", false,-1);
        tracep->declBit(c+315,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_csr_skip", false,-1);
        tracep->declBit(c+338,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_mem_read", false,-1);
        tracep->declQuad(c+155,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_pc", false,-1, 63,0);
        tracep->declBus(c+157,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_inst", false,-1, 31,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_opcode", false,-1, 6,0);
        tracep->declBus(c+170,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_s_imm", false,-1, 6,0);
        tracep->declBus(c+171,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_s_imm_s", false,-1, 4,0);
        tracep->declQuad(c+158,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_op1", false,-1, 63,0);
        tracep->declQuad(c+160,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_op2", false,-1, 63,0);
        tracep->declBus(c+168,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_I_imm", false,-1, 11,0);
        tracep->declBus(c+97,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_s1", false,-1, 2,0);
        tracep->declBus(c+162,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_rd", false,-1, 4,0);
        tracep->declBit(c+184,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_w_ena", false,-1);
        tracep->declQuad(c+43,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_csr_data", false,-1, 63,0);
        tracep->declBit(c+180,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_csr_read", false,-1);
        tracep->declBit(c+181,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_csr_write", false,-1);
        tracep->declBus(c+178,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_csr", false,-1, 11,0);
        tracep->declQuad(c+45,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_data", false,-1, 63,0);
        tracep->declBit(c+47,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_mem_en", false,-1);
        tracep->declBit(c+923,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_open", false,-1);
        tracep->declBit(c+85,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM exe_skip", false,-1);
        tracep->declQuad(c+186,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_pc", false,-1, 63,0);
        tracep->declBus(c+188,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_inst", false,-1, 31,0);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_fetched", false,-1);
        tracep->declBit(c+316,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_csr_skip", false,-1);
        tracep->declBus(c+189,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_opcode", false,-1, 6,0);
        tracep->declBus(c+190,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_s_imm", false,-1, 6,0);
        tracep->declBus(c+191,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_s_imm_s", false,-1, 4,0);
        tracep->declQuad(c+192,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_op1", false,-1, 63,0);
        tracep->declQuad(c+194,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_op2", false,-1, 63,0);
        tracep->declBus(c+196,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_I_imm", false,-1, 11,0);
        tracep->declBus(c+211,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_rd", false,-1, 4,0);
        tracep->declBit(c+200,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_w_ena", false,-1);
        tracep->declQuad(c+201,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_csr_data", false,-1, 63,0);
        tracep->declBit(c+203,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_csr_read", false,-1);
        tracep->declBit(c+204,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_csr_write", false,-1);
        tracep->declBit(c+339,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_mem_read", false,-1);
        tracep->declBus(c+205,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_csr", false,-1, 11,0);
        tracep->declQuad(c+198,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_data", false,-1, 63,0);
        tracep->declBus(c+197,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_s1", false,-1, 2,0);
        tracep->declBit(c+185,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_open", false,-1);
        tracep->declBit(c+206,"SimTop ysyx_210448_u_cpu ysyx_210448_EXE_MEM mem_skip", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage rst", false,-1);
        tracep->declBus(c+111,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage axi_r_id_i", false,-1, 3,0);
        tracep->declBit(c+114,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage axi_mem_write", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage axi_read_ready", false,-1);
        tracep->declBit(c+84,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage handshake_done", false,-1);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_fetched", false,-1);
        tracep->declBit(c+185,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_open", false,-1);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_read", false,-1);
        tracep->declBit(c+125,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage stop", false,-1);
        tracep->declBit(c+334,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage wb_write", false,-1);
        tracep->declBus(c+341,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage s3", false,-1, 2,0);
        tracep->declQuad(c+186,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_pc", false,-1, 63,0);
        tracep->declBus(c+188,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_inst", false,-1, 31,0);
        tracep->declBus(c+211,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_rd", false,-1, 4,0);
        tracep->declBus(c+189,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_opcode", false,-1, 6,0);
        tracep->declBus(c+163,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage exe_opcode", false,-1, 6,0);
        tracep->declBus(c+190,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_s_imm", false,-1, 6,0);
        tracep->declBus(c+191,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_s_imm_s", false,-1, 4,0);
        tracep->declQuad(c+192,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_op1", false,-1, 63,0);
        tracep->declQuad(c+194,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_op2", false,-1, 63,0);
        tracep->declBus(c+196,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_I_imm", false,-1, 11,0);
        tracep->declBus(c+197,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_s1", false,-1, 2,0);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_write", false,-1);
        tracep->declBit(c+342,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage wb_write_ready", false,-1);
        tracep->declBit(c+12,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage b_hs", false,-1);
        tracep->declQuad(c+326,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_read_addr", false,-1, 63,0);
        tracep->declQuad(c+328,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage rdata", false,-1, 63,0);
        tracep->declQuad(c+109,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_write_addr", false,-1, 63,0);
        tracep->declQuad(c+107,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage wdata", false,-1, 63,0);
        tracep->declBus(c+93,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage wmask", false,-1, 7,0);
        tracep->declBit(c+343,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_write_ready", false,-1);
        tracep->declQuad(c+207,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_read_data", false,-1, 63,0);
        tracep->declBit(c+212,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_wb_en", false,-1);
        tracep->declBus(c+936,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_read_id", false,-1, 3,0);
        tracep->declBus(c+421,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage s_s", false,-1, 11,0);
        tracep->declQuad(c+194,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_data", false,-1, 63,0);
        tracep->declBus(c+422,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage s4", false,-1, 2,0);
        tracep->declBus(c+956,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage s5", false,-1, 2,0);
        tracep->declBus(c+957,"SimTop ysyx_210448_u_cpu ysyx_210448_mem_stage mem_I_imm_I", false,-1, 11,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB rst", false,-1);
        tracep->declBit(c+212,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_wb_en", false,-1);
        tracep->declBit(c+99,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_write", false,-1);
        tracep->declBit(c+343,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_write_ready", false,-1);
        tracep->declQuad(c+186,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_pc", false,-1, 63,0);
        tracep->declBus(c+188,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_inst", false,-1, 31,0);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_fetched", false,-1);
        tracep->declBit(c+200,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_w_ena", false,-1);
        tracep->declBus(c+211,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_rd", false,-1, 4,0);
        tracep->declQuad(c+198,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_data", false,-1, 63,0);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_read", false,-1);
        tracep->declQuad(c+207,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_read_data", false,-1, 63,0);
        tracep->declBus(c+205,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_csr", false,-1, 11,0);
        tracep->declBit(c+204,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_csr_write", false,-1);
        tracep->declBit(c+203,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_csr_read", false,-1);
        tracep->declQuad(c+201,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_csr_data", false,-1, 63,0);
        tracep->declBus(c+189,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_opcode", false,-1, 6,0);
        tracep->declBit(c+185,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_open", false,-1);
        tracep->declBit(c+940,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB close", false,-1);
        tracep->declBit(c+206,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_skip", false,-1);
        tracep->declBit(c+316,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB mem_csr_skip", false,-1);
        tracep->declQuad(c+213,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_pc", false,-1, 63,0);
        tracep->declBus(c+215,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_inst", false,-1, 31,0);
        tracep->declBit(c+325,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_fetched", false,-1);
        tracep->declBit(c+342,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_write_ready", false,-1);
        tracep->declBit(c+216,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_w_ena", false,-1);
        tracep->declBit(c+334,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_write", false,-1);
        tracep->declBus(c+217,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_rd", false,-1, 4,0);
        tracep->declQuad(c+218,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_data", false,-1, 63,0);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_read", false,-1);
        tracep->declQuad(c+221,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_read_data", false,-1, 63,0);
        tracep->declBus(c+223,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_csr", false,-1, 11,0);
        tracep->declBit(c+224,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_csr_write", false,-1);
        tracep->declBit(c+225,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_csr_read", false,-1);
        tracep->declQuad(c+226,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_csr_data", false,-1, 63,0);
        tracep->declBus(c+228,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_opcode", false,-1, 6,0);
        tracep->declBit(c+210,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_open", false,-1);
        tracep->declBit(c+209,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_skip", false,-1);
        tracep->declBit(c+335,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_close", false,-1);
        tracep->declBit(c+317,"SimTop ysyx_210448_u_cpu ysyx_210448_MEM_WB wb_csr_skip", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage rst", false,-1);
        tracep->declBit(c+346,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ld", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage if_pc", false,-1, 63,0);
        tracep->declBus(c+215,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_inst", false,-1, 31,0);
        tracep->declBit(c+42,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage exe_pc_write", false,-1);
        tracep->declQuad(c+51,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage exe_pc_add", false,-1, 63,0);
        tracep->declBit(c+116,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage clint_skip", false,-1);
        tracep->declBit(c+149,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_ena1", false,-1);
        tracep->declBit(c+150,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_ena2", false,-1);
        tracep->declBit(c+126,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage if_fetched", false,-1);
        tracep->declBit(c+325,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_fetched", false,-1);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage exe_fetched", false,-1);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mem_fetched", false,-1);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mem_read", false,-1);
        tracep->declBit(c+184,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage exe_w_ena", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage if_ar_hand", false,-1);
        tracep->declBit(c+332,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage axi_mem_read", false,-1);
        tracep->declBit(c+114,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage axi_mem_write", false,-1);
        tracep->declQuad(c+873,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtime_open", false,-1);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_rs2", false,-1, 4,0);
        tracep->declBit(c+344,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage if_w_ena", false,-1);
        tracep->declBit(c+210,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_open", false,-1);
        tracep->declQuad(c+213,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_pc", false,-1, 63,0);
        tracep->declBit(c+216,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_w_ena", false,-1);
        tracep->declBus(c+217,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_rd", false,-1, 4,0);
        tracep->declQuad(c+218,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_data", false,-1, 63,0);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_read", false,-1);
        tracep->declBit(c+335,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_close", false,-1);
        tracep->declQuad(c+221,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_read_data", false,-1, 63,0);
        tracep->declBus(c+223,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_csr", false,-1, 11,0);
        tracep->declBus(c+146,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_csr", false,-1, 11,0);
        tracep->declBit(c+224,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_csr_write", false,-1);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_csr_read", false,-1);
        tracep->declQuad(c+226,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_csr_data", false,-1, 63,0);
        tracep->declQuad(c+881,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_op1", false,-1, 63,0);
        tracep->declQuad(c+883,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_op2", false,-1, 63,0);
        tracep->declQuad(c+885,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_t", false,-1, 63,0);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+423+i*2,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage regs_o", true,(i+0), 63,0);}}
        tracep->declQuad(c+295,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mstatus", false,-1, 63,0);
        tracep->declQuad(c+313,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage sstatus", false,-1, 63,0);
        tracep->declQuad(c+297,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mepc", false,-1, 63,0);
        tracep->declQuad(c+299,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtvec", false,-1, 63,0);
        tracep->declQuad(c+301,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mcause", false,-1, 63,0);
        tracep->declQuad(c+318,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mhartid", false,-1, 63,0);
        tracep->declQuad(c+303,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mip", false,-1, 63,0);
        tracep->declQuad(c+305,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mie", false,-1, 63,0);
        tracep->declQuad(c+309,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mcycle", false,-1, 63,0);
        tracep->declQuad(c+311,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mscratch", false,-1, 63,0);
        tracep->declBit(c+50,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage id_csr_skip", false,-1);
        tracep->declQuad(c+48,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mcause_data", false,-1, 63,0);
        tracep->declQuad(c+932,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mstatus_data", false,-1, 63,0);
        tracep->declQuad(c+307,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage rmstatus", false,-1, 63,0);
        tracep->declQuad(c+320,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage csr_pc_add", false,-1, 63,0);
        tracep->declBit(c+322,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage csr_pc_write", false,-1);
        tracep->declBit(c+230,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage wb_ok", false,-1);
        tracep->declBit(c+340,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ena1", false,-1);
        tracep->declBit(c+229,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ena2", false,-1);
        tracep->declBit(c+53,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage clock_interrupt", false,-1);
        tracep->declQuad(c+487,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtimecmp", false,-1, 63,0);
        tracep->declQuad(c+489,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage mtime", false,-1, 63,0);
        tracep->declBit(c+491,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage w_ena", false,-1);
        tracep->declBus(c+492,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage w_rd", false,-1, 4,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR rst", false,-1);
        tracep->declBit(c+126,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR if_fetched", false,-1);
        tracep->declBit(c+325,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_fetched", false,-1);
        tracep->declBit(c+324,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR exe_fetched", false,-1);
        tracep->declBit(c+42,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR exe_pc_write", false,-1);
        tracep->declBit(c+103,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR if_ar_hand", false,-1);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_read", false,-1);
        tracep->declBit(c+98,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mem_fetched", false,-1);
        tracep->declBit(c+96,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mem_read", false,-1);
        tracep->declQuad(c+123,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR if_pc", false,-1, 63,0);
        tracep->declQuad(c+51,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR exe_pc_add", false,-1, 63,0);
        tracep->declBus(c+215,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_inst", false,-1, 31,0);
        tracep->declBus(c+146,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR id_csr", false,-1, 11,0);
        tracep->declBus(c+223,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_csr", false,-1, 11,0);
        tracep->declBit(c+224,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_csr_write", false,-1);
        tracep->declBit(c+148,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR id_csr_read", false,-1);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR id_rs1", false,-1, 4,0);
        tracep->declBus(c+217,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_rd", false,-1, 4,0);
        tracep->declQuad(c+873,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtime_open", false,-1);
        tracep->declBit(c+116,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR clint_skip", false,-1);
        tracep->declQuad(c+226,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR csr_data", false,-1, 63,0);
        tracep->declQuad(c+213,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR pc", false,-1, 63,0);
        tracep->declQuad(c+885,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR id_t", false,-1, 63,0);
        tracep->declQuad(c+295,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mstatus", false,-1, 63,0);
        tracep->declQuad(c+313,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR sstatus", false,-1, 63,0);
        tracep->declQuad(c+297,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mepc", false,-1, 63,0);
        tracep->declQuad(c+299,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtvec", false,-1, 63,0);
        tracep->declQuad(c+301,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mcause", false,-1, 63,0);
        tracep->declQuad(c+303,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mip", false,-1, 63,0);
        tracep->declQuad(c+305,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mie", false,-1, 63,0);
        tracep->declQuad(c+309,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mcycle", false,-1, 63,0);
        tracep->declQuad(c+311,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mscratch", false,-1, 63,0);
        tracep->declBit(c+50,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR id_csr_skip", false,-1);
        tracep->declQuad(c+48,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mcause_data", false,-1, 63,0);
        tracep->declQuad(c+932,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mstatus_data", false,-1, 63,0);
        tracep->declQuad(c+307,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR rmstatus", false,-1, 63,0);
        tracep->declQuad(c+318,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mhartid", false,-1, 63,0);
        tracep->declQuad(c+320,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR csr_pc_add", false,-1, 63,0);
        tracep->declBit(c+322,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR csr_pc_write", false,-1);
        tracep->declQuad(c+487,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtimecmp", false,-1, 63,0);
        tracep->declQuad(c+489,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mtime", false,-1, 63,0);
        tracep->declBit(c+53,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR clock_interrupt", false,-1);
        tracep->declBit(c+493,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR interrupt_ready1", false,-1);
        tracep->declBit(c+81,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR interrupt", false,-1);
        tracep->declBit(c+958,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR pc_write_ready", false,-1);
        tracep->declQuad(c+959,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR pc_add_ready", false,-1, 63,0);
        tracep->declBit(c+494,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR wb_stage", false,-1);
        tracep->declQuad(c+495,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mepc_exe", false,-1, 63,0);
        tracep->declBit(c+961,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR pc_jump", false,-1);
        tracep->declBit(c+497,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mstatus_mie", false,-1);
        tracep->declBit(c+498,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mstatus_mpie", false,-1);
        tracep->declBus(c+912,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mpp", false,-1, 1,0);
        tracep->declBus(c+499,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR mstatus_fs", false,-1, 1,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint rst", false,-1);
        tracep->declQuad(c+873,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtimecmp_data", false,-1, 63,0);
        tracep->declBit(c+16,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtimecmp_open", false,-1);
        tracep->declQuad(c+875,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtime_data", false,-1, 63,0);
        tracep->declBit(c+17,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtime_open", false,-1);
        tracep->declQuad(c+48,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mcause_data", false,-1, 63,0);
        tracep->declQuad(c+295,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mstatus", false,-1, 63,0);
        tracep->declQuad(c+305,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mie", false,-1, 63,0);
        tracep->declQuad(c+487,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtimecmp", false,-1, 63,0);
        tracep->declQuad(c+489,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint mtime", false,-1, 63,0);
        tracep->declBit(c+53,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_CSR ysyx_210448_clint clock_interrupt", false,-1);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile clk", false,-1);
        tracep->declBit(c+800,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile rst", false,-1);
        tracep->declBit(c+220,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile read", false,-1);
        tracep->declBit(c+346,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile ld", false,-1);
        tracep->declQuad(c+221,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile read_data", false,-1, 63,0);
        tracep->declBus(c+492,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile w_addr", false,-1, 4,0);
        tracep->declQuad(c+218,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile data", false,-1, 63,0);
        tracep->declBit(c+491,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile w_ena", false,-1);
        tracep->declBus(c+151,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile rs1", false,-1, 4,0);
        tracep->declBus(c+152,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile rs2", false,-1, 4,0);
        tracep->declBit(c+340,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile ena1", false,-1);
        tracep->declBit(c+229,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile ena2", false,-1);
        tracep->declQuad(c+881,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile op1", false,-1, 63,0);
        tracep->declQuad(c+883,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile op2", false,-1, 63,0);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+500+i*2,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile regs_o", true,(i+0), 63,0);}}
        tracep->declQuad(c+564,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile w_data", false,-1, 63,0);
        {int i; for (i=0; i<32; i++) {
                tracep->declQuad(c+566+i*2,"SimTop ysyx_210448_u_cpu ysyx_210448_wb_stage ysyx_210448_Regfile regs", true,(i+0), 63,0);}}
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestInstrCommit clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestInstrCommit coreid", false,-1, 7,0);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestInstrCommit index", false,-1, 7,0);
        tracep->declBit(c+637,"SimTop ysyx_210448_u_cpu DifftestInstrCommit valid", false,-1);
        tracep->declQuad(c+634,"SimTop ysyx_210448_u_cpu DifftestInstrCommit pc", false,-1, 63,0);
        tracep->declBus(c+636,"SimTop ysyx_210448_u_cpu DifftestInstrCommit instr", false,-1, 31,0);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestInstrCommit special", false,-1, 7,0);
        tracep->declBit(c+644,"SimTop ysyx_210448_u_cpu DifftestInstrCommit skip", false,-1);
        tracep->declBit(c+905,"SimTop ysyx_210448_u_cpu DifftestInstrCommit isRVC", false,-1);
        tracep->declBit(c+905,"SimTop ysyx_210448_u_cpu DifftestInstrCommit scFailed", false,-1);
        tracep->declBit(c+630,"SimTop ysyx_210448_u_cpu DifftestInstrCommit wen", false,-1);
        tracep->declBus(c+631,"SimTop ysyx_210448_u_cpu DifftestInstrCommit wdest", false,-1, 7,0);
        tracep->declQuad(c+632,"SimTop ysyx_210448_u_cpu DifftestInstrCommit wdata", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestArchEvent clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestArchEvent coreid", false,-1, 7,0);
        tracep->declBus(c+709,"SimTop ysyx_210448_u_cpu DifftestArchEvent intrNO", false,-1, 31,0);
        tracep->declBus(c+710,"SimTop ysyx_210448_u_cpu DifftestArchEvent cause", false,-1, 31,0);
        tracep->declQuad(c+297,"SimTop ysyx_210448_u_cpu DifftestArchEvent exceptionPC", false,-1, 63,0);
        tracep->declBus(c+636,"SimTop ysyx_210448_u_cpu DifftestArchEvent exceptionInst", false,-1, 31,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState coreid", false,-1, 7,0);
        tracep->declQuad(c+734,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_0", false,-1, 63,0);
        tracep->declQuad(c+736,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_1", false,-1, 63,0);
        tracep->declQuad(c+738,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_2", false,-1, 63,0);
        tracep->declQuad(c+740,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_3", false,-1, 63,0);
        tracep->declQuad(c+742,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_4", false,-1, 63,0);
        tracep->declQuad(c+744,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_5", false,-1, 63,0);
        tracep->declQuad(c+746,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_6", false,-1, 63,0);
        tracep->declQuad(c+748,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_7", false,-1, 63,0);
        tracep->declQuad(c+750,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_8", false,-1, 63,0);
        tracep->declQuad(c+752,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_9", false,-1, 63,0);
        tracep->declQuad(c+754,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_10", false,-1, 63,0);
        tracep->declQuad(c+756,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_11", false,-1, 63,0);
        tracep->declQuad(c+758,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_12", false,-1, 63,0);
        tracep->declQuad(c+760,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_13", false,-1, 63,0);
        tracep->declQuad(c+762,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_14", false,-1, 63,0);
        tracep->declQuad(c+764,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_15", false,-1, 63,0);
        tracep->declQuad(c+766,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_16", false,-1, 63,0);
        tracep->declQuad(c+768,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_17", false,-1, 63,0);
        tracep->declQuad(c+770,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_18", false,-1, 63,0);
        tracep->declQuad(c+772,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_19", false,-1, 63,0);
        tracep->declQuad(c+774,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_20", false,-1, 63,0);
        tracep->declQuad(c+776,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_21", false,-1, 63,0);
        tracep->declQuad(c+778,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_22", false,-1, 63,0);
        tracep->declQuad(c+780,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_23", false,-1, 63,0);
        tracep->declQuad(c+782,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_24", false,-1, 63,0);
        tracep->declQuad(c+784,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_25", false,-1, 63,0);
        tracep->declQuad(c+786,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_26", false,-1, 63,0);
        tracep->declQuad(c+788,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_27", false,-1, 63,0);
        tracep->declQuad(c+790,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_28", false,-1, 63,0);
        tracep->declQuad(c+792,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_29", false,-1, 63,0);
        tracep->declQuad(c+794,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_30", false,-1, 63,0);
        tracep->declQuad(c+796,"SimTop ysyx_210448_u_cpu DifftestArchIntRegState gpr_31", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestTrapEvent clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestTrapEvent coreid", false,-1, 7,0);
        tracep->declBit(c+638,"SimTop ysyx_210448_u_cpu DifftestTrapEvent valid", false,-1);
        tracep->declBus(c+798,"SimTop ysyx_210448_u_cpu DifftestTrapEvent code", false,-1, 2,0);
        tracep->declQuad(c+634,"SimTop ysyx_210448_u_cpu DifftestTrapEvent pc", false,-1, 63,0);
        tracep->declQuad(c+640,"SimTop ysyx_210448_u_cpu DifftestTrapEvent cycleCnt", false,-1, 63,0);
        tracep->declQuad(c+642,"SimTop ysyx_210448_u_cpu DifftestTrapEvent instrCnt", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestCSRState clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestCSRState coreid", false,-1, 7,0);
        tracep->declBus(c+912,"SimTop ysyx_210448_u_cpu DifftestCSRState priviledgeMode", false,-1, 1,0);
        tracep->declQuad(c+713,"SimTop ysyx_210448_u_cpu DifftestCSRState mstatus", false,-1, 63,0);
        tracep->declQuad(c+715,"SimTop ysyx_210448_u_cpu DifftestCSRState sstatus", false,-1, 63,0);
        tracep->declQuad(c+717,"SimTop ysyx_210448_u_cpu DifftestCSRState mepc", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState sepc", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState mtval", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState stval", false,-1, 63,0);
        tracep->declQuad(c+711,"SimTop ysyx_210448_u_cpu DifftestCSRState mtvec", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState stvec", false,-1, 63,0);
        tracep->declQuad(c+719,"SimTop ysyx_210448_u_cpu DifftestCSRState mcause", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState scause", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState satp", false,-1, 63,0);
        tracep->declQuad(c+721,"SimTop ysyx_210448_u_cpu DifftestCSRState mip", false,-1, 63,0);
        tracep->declQuad(c+723,"SimTop ysyx_210448_u_cpu DifftestCSRState mie", false,-1, 63,0);
        tracep->declQuad(c+725,"SimTop ysyx_210448_u_cpu DifftestCSRState mscratch", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState sscratch", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState mideleg", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestCSRState medeleg", false,-1, 63,0);
        tracep->declBit(c+799,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState clock", false,-1);
        tracep->declBus(c+962,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState coreid", false,-1, 7,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_0", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_1", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_2", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_3", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_4", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_5", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_6", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_7", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_8", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_9", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_10", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_11", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_12", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_13", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_14", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_15", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_16", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_17", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_18", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_19", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_20", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_21", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_22", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_23", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_24", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_25", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_26", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_27", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_28", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_29", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_30", false,-1, 63,0);
        tracep->declQuad(c+963,"SimTop ysyx_210448_u_cpu DifftestArchFpRegState fpr_31", false,-1, 63,0);
    }
}

void VSimTop::traceRegister(VerilatedVcd* tracep) {
    // Body
    {
        tracep->addFullCb(&traceFullTop0, __VlSymsp);
        tracep->addChgCb(&traceChgTop0, __VlSymsp);
        tracep->addCleanupCb(&traceCleanup, __VlSymsp);
    }
}

void VSimTop::traceFullTop0(void* userp, VerilatedVcd* tracep) {
    VSimTop__Syms* __restrict vlSymsp = static_cast<VSimTop__Syms*>(userp);
    VSimTop* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    {
        vlTOPp->traceFullSub0(userp, tracep);
    }
}

void VSimTop::traceFullSub0(void* userp, VerilatedVcd* tracep) {
    VSimTop__Syms* __restrict vlSymsp = static_cast<VSimTop__Syms*>(userp);
    VSimTop* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    vluint32_t* const oldp = tracep->oldp(vlSymsp->__Vm_baseCode);
    if (false && oldp) {}  // Prevent unused
    // Body
    {
        tracep->fullCData(oldp+1,(vlTOPp->SimTop__DOT__axi_size),2);
        tracep->fullBit(oldp+2,((0U == (IData)(vlTOPp->SimTop__DOT__axi_size))));
        tracep->fullBit(oldp+3,((1U == (IData)(vlTOPp->SimTop__DOT__axi_size))));
        tracep->fullBit(oldp+4,((2U == (IData)(vlTOPp->SimTop__DOT__axi_size))));
        tracep->fullBit(oldp+5,((3U == (IData)(vlTOPp->SimTop__DOT__axi_size))));
        tracep->fullCData(oldp+6,((((1U & (- (IData)(
                                                     (1U 
                                                      == (IData)(vlTOPp->SimTop__DOT__axi_size))))) 
                                    | (3U & (- (IData)(
                                                       (2U 
                                                        == (IData)(vlTOPp->SimTop__DOT__axi_size)))))) 
                                   | (7U & (- (IData)(
                                                      (3U 
                                                       == (IData)(vlTOPp->SimTop__DOT__axi_size))))))),4);
        tracep->fullCData(oldp+7,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__axi_len),8);
        tracep->fullBit(oldp+8,(vlTOPp->SimTop__DOT__ar_valid));
        tracep->fullQData(oldp+9,((0xfffffffffffffff8ULL 
                                   & vlTOPp->SimTop__DOT__axi_read_addr)),64);
        tracep->fullBit(oldp+11,(vlTOPp->SimTop__DOT__r_hs));
        tracep->fullBit(oldp+12,(vlTOPp->SimTop__DOT__b_hs));
        tracep->fullBit(oldp+13,(vlTOPp->SimTop__DOT__axi_read_valid));
        tracep->fullQData(oldp+14,(vlTOPp->SimTop__DOT__axi_read_addr),64);
        tracep->fullBit(oldp+16,(vlTOPp->SimTop__DOT__mtimecmp_open));
        tracep->fullBit(oldp+17,(vlTOPp->SimTop__DOT__mtime_open));
        tracep->fullBit(oldp+18,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__aw_hs));
        tracep->fullBit(oldp+19,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_hs));
        tracep->fullBit(oldp+20,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__ar_hs));
        tracep->fullBit(oldp+21,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_done));
        tracep->fullBit(oldp+22,((0U == (7U & (IData)(vlTOPp->SimTop__DOT__axi_read_addr)))));
        tracep->fullCData(oldp+23,((7U & (IData)(vlTOPp->SimTop__DOT__axi_read_addr))),4);
        tracep->fullCData(oldp+24,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__addr_end),4);
        tracep->fullBit(oldp+25,((1U & ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__addr_end) 
                                        >> 3U))));
        tracep->fullCData(oldp+26,((0x38U & ((IData)(vlTOPp->SimTop__DOT__axi_read_addr) 
                                             << 3U))),6);
        tracep->fullCData(oldp+27,((0x3fU & ((IData)(0x3fU) 
                                             - (0x38U 
                                                & ((IData)(vlTOPp->SimTop__DOT__axi_read_addr) 
                                                   << 3U))))),6);
        tracep->fullWData(oldp+28,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask),128);
        tracep->fullQData(oldp+32,((((QData)((IData)(
                                                     vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[1U])) 
                                     << 0x20U) | (QData)((IData)(
                                                                 vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[0U])))),64);
        tracep->fullQData(oldp+34,((((QData)((IData)(
                                                     vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[3U])) 
                                     << 0x20U) | (QData)((IData)(
                                                                 vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[2U])))),64);
        tracep->fullQData(oldp+36,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__axi_r_data_l),64);
        tracep->fullBit(oldp+38,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_exe_bubble));
        tracep->fullQData(oldp+39,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__pc_add),64);
        tracep->fullBit(oldp+41,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__pc_write));
        tracep->fullBit(oldp+42,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc_write));
        tracep->fullQData(oldp+43,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_data),64);
        tracep->fullQData(oldp+45,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_data),64);
        tracep->fullBit(oldp+47,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_mem_en));
        tracep->fullQData(oldp+48,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_data),64);
        tracep->fullBit(oldp+50,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr_skip));
        tracep->fullQData(oldp+51,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc_add),64);
        tracep->fullBit(oldp+53,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__clock_interrupt));
        tracep->fullQData(oldp+54,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_if_stage__DOT__if_inst_data),64);
        tracep->fullQData(oldp+56,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_u_imm_u),64);
        tracep->fullQData(oldp+58,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_b_imm_b_b_b),64);
        tracep->fullSData(oldp+60,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_b_imm_b_b),12);
        tracep->fullIData(oldp+61,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__jal_imm),20);
        tracep->fullBit(oldp+62,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm1));
        tracep->fullCData(oldp+63,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm2),8);
        tracep->fullBit(oldp+64,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm3));
        tracep->fullSData(oldp+65,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm4),10);
        tracep->fullCData(oldp+66,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm5),6);
        tracep->fullCData(oldp+67,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm6),4);
        tracep->fullCData(oldp+68,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sra_imm),6);
        tracep->fullCData(oldp+69,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sra_imm_w),5);
        tracep->fullCData(oldp+70,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sll_imm),5);
        tracep->fullCData(oldp+71,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sll_imm_sll),6);
        tracep->fullCData(oldp+72,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srl_imm),6);
        tracep->fullCData(oldp+73,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srl_imm_w),5);
        tracep->fullQData(oldp+74,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sllw),64);
        tracep->fullIData(oldp+76,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srlw),32);
        tracep->fullIData(oldp+77,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sraw),32);
        tracep->fullCData(oldp+78,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__printf),8);
        tracep->fullQData(oldp+79,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__csr_zimm),64);
        tracep->fullBit(oldp+81,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__interrupt));
        tracep->fullBit(oldp+82,((((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__len) 
                                   != (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__axi_len)) 
                                  & ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_hs) 
                                     | (IData)(vlTOPp->SimTop__DOT__r_hs)))));
        tracep->fullBit(oldp+83,(((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_done) 
                                  | (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_ready))));
        tracep->fullBit(oldp+84,(((IData)(vlTOPp->SimTop__DOT__axi_read_valid) 
                                  & (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_ready))));
        tracep->fullBit(oldp+85,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_skip));
        tracep->fullBit(oldp+86,(((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__clock_interrupt)
                                   ? 0U : ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_fetched)
                                            ? 1U : 0U))));
        tracep->fullBit(oldp+87,((1U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state))));
        tracep->fullQData(oldp+88,((0xfffffffffffffff8ULL 
                                    & vlTOPp->SimTop__DOT__axi_write_addr)),64);
        tracep->fullBit(oldp+90,((2U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state))));
        tracep->fullQData(oldp+91,(vlTOPp->SimTop__DOT__w_data),64);
        tracep->fullCData(oldp+93,(vlTOPp->SimTop__DOT__axi_write_mask),8);
        tracep->fullBit(oldp+94,((3U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state))));
        tracep->fullBit(oldp+95,((2U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state))));
        tracep->fullBit(oldp+96,(vlTOPp->SimTop__DOT__mem_read));
        tracep->fullCData(oldp+97,(vlTOPp->SimTop__DOT__exe_s1),3);
        tracep->fullBit(oldp+98,(vlTOPp->SimTop__DOT__mem_fetched));
        tracep->fullBit(oldp+99,(vlTOPp->SimTop__DOT__mem_write));
        tracep->fullQData(oldp+100,(vlTOPp->SimTop__DOT__if_addr),64);
        tracep->fullIData(oldp+102,(vlTOPp->SimTop__DOT__if_inst),32);
        tracep->fullBit(oldp+103,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_ready));
        tracep->fullQData(oldp+104,(vlTOPp->SimTop__DOT__axi_data_read),64);
        tracep->fullCData(oldp+106,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_resp),2);
        tracep->fullQData(oldp+107,(vlTOPp->SimTop__DOT__axi_write_data),64);
        tracep->fullQData(oldp+109,(vlTOPp->SimTop__DOT__axi_write_addr),64);
        tracep->fullCData(oldp+111,(vlTOPp->SimTop__DOT__axi_r_id_o),4);
        tracep->fullQData(oldp+112,(vlTOPp->SimTop__DOT__mem_read_data),64);
        tracep->fullBit(oldp+114,(((0x23U == (0x7fU 
                                              & vlTOPp->SimTop__DOT__if_inst))
                                    ? 1U : 0U)));
        tracep->fullBit(oldp+115,(vlTOPp->SimTop__DOT__axi_r_hs_o));
        tracep->fullBit(oldp+116,(vlTOPp->SimTop__DOT__clint_skip));
        tracep->fullCData(oldp+117,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state),2);
        tracep->fullCData(oldp+118,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state),2);
        tracep->fullBit(oldp+119,((0U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state))));
        tracep->fullBit(oldp+120,((0U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state))));
        tracep->fullBit(oldp+121,((1U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state))));
        tracep->fullCData(oldp+122,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__len),8);
        tracep->fullQData(oldp+123,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_pc),64);
        tracep->fullBit(oldp+125,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_stop));
        tracep->fullBit(oldp+126,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_fetched));
        tracep->fullQData(oldp+127,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_pc),64);
        tracep->fullIData(oldp+129,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst),32);
        tracep->fullCData(oldp+130,((((((((((((0x37U 
                                               == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)) 
                                              | (0x17U 
                                                 == 
                                                 (0x7fU 
                                                  & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                             | (0x6fU 
                                                == 
                                                (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                            | (3U == 
                                               (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                           | (0x13U 
                                              == (0x7fU 
                                                  & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                          | (0x33U 
                                             == (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                         | (0x67U == 
                                            (0x7fU 
                                             & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                        | (0x1bU == 
                                           (0x7fU & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                       | (0x3bU == 
                                          (0x7fU & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                      | (0x73U == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)))
                                      ? (0x1fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 7U))
                                      : 0U)),5);
        tracep->fullCData(oldp+131,((0x7fU & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)),7);
        tracep->fullIData(oldp+132,((((0x37U == (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)) 
                                      | (0x17U == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)))
                                      ? (0xfffffU & 
                                         (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                          >> 0xcU))
                                      : 0U)),20);
        tracep->fullIData(oldp+133,(((0x6fU == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0xfffffU & 
                                         (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                          >> 0xcU))
                                      : 0U)),20);
        tracep->fullSData(oldp+134,(((0x67U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0xfffU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                   >> 0x14U))
                                      : 0U)),12);
        tracep->fullSData(oldp+135,(((0x13U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0xfffU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                   >> 0x14U))
                                      : 0U)),12);
        tracep->fullSData(oldp+136,(((3U == (0x7fU 
                                             & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0xfffU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                   >> 0x14U))
                                      : 0U)),12);
        tracep->fullCData(oldp+137,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_b_imm),7);
        tracep->fullCData(oldp+138,(((0x23U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x7fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 0x19U))
                                      : 0U)),7);
        tracep->fullCData(oldp+139,(((0x23U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x1fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 7U))
                                      : 0U)),5);
        tracep->fullCData(oldp+140,(((0x63U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x1fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 7U))
                                      : 0U)),5);
        tracep->fullSData(oldp+141,(((0x1bU == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0xfffU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                   >> 0x14U))
                                      : 0U)),12);
        tracep->fullCData(oldp+142,(((0x1bU == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x3fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 0x14U))
                                      : 0U)),6);
        tracep->fullCData(oldp+143,((((((((((3U == 
                                             (0x7fU 
                                              & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)) 
                                            | (0x13U 
                                               == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                           | (0x63U 
                                              == (0x7fU 
                                                  & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                          | (0x23U 
                                             == (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                         | (0x33U == 
                                            (0x7fU 
                                             & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                        | (0x3bU == 
                                           (0x7fU & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                       | (0x1bU == 
                                          (0x7fU & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                      | (0x73U == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)))
                                      ? (7U & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                               >> 0xcU))
                                      : 0U)),3);
        tracep->fullBit(oldp+144,((((((0x13U == (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)) 
                                      | (0x33U == (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                     | (0x3bU == (0x7fU 
                                                  & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))) 
                                    | (0x1bU == (0x7fU 
                                                 & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst)))
                                    ? (1U & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                             >> 0x1eU))
                                    : 0U)));
        tracep->fullCData(oldp+145,(((0x13U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x3fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 0x14U))
                                      : 0U)),6);
        tracep->fullSData(oldp+146,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr),12);
        tracep->fullCData(oldp+147,(((0x73U == (0x7fU 
                                                & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                      ? (0x1fU & (vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst 
                                                  >> 0xfU))
                                      : 0U)),5);
        tracep->fullBit(oldp+148,(((0x73U == (0x7fU 
                                              & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                    ? 1U : 0U)));
        tracep->fullBit(oldp+149,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1));
        tracep->fullBit(oldp+150,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2));
        tracep->fullCData(oldp+151,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1),5);
        tracep->fullCData(oldp+152,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2),5);
        tracep->fullCData(oldp+153,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__rs1),5);
        tracep->fullCData(oldp+154,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__rs2),5);
        tracep->fullQData(oldp+155,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc),64);
        tracep->fullIData(oldp+157,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_inst),32);
        tracep->fullQData(oldp+158,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_op1),64);
        tracep->fullQData(oldp+160,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_op2),64);
        tracep->fullCData(oldp+162,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_rd),5);
        tracep->fullCData(oldp+163,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_opcode),7);
        tracep->fullIData(oldp+164,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_u_imm),20);
        tracep->fullIData(oldp+165,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_j_imm),20);
        tracep->fullSData(oldp+166,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_j_imm_j),12);
        tracep->fullSData(oldp+167,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_i_imm),12);
        tracep->fullSData(oldp+168,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_I_imm),12);
        tracep->fullCData(oldp+169,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_b_imm),7);
        tracep->fullCData(oldp+170,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s_imm),7);
        tracep->fullCData(oldp+171,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s_imm_s),5);
        tracep->fullCData(oldp+172,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_i_imm_i),5);
        tracep->fullCData(oldp+173,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_b_imm_b),5);
        tracep->fullSData(oldp+174,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_imm),12);
        tracep->fullCData(oldp+175,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_shamt),6);
        tracep->fullBit(oldp+176,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s2));
        tracep->fullCData(oldp+177,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__shamt),6);
        tracep->fullSData(oldp+178,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr),12);
        tracep->fullCData(oldp+179,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_zimm),5);
        tracep->fullBit(oldp+180,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_read));
        tracep->fullBit(oldp+181,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_write));
        tracep->fullQData(oldp+182,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_t),64);
        tracep->fullBit(oldp+184,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena));
        tracep->fullBit(oldp+185,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_open));
        tracep->fullQData(oldp+186,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_pc),64);
        tracep->fullIData(oldp+188,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_inst),32);
        tracep->fullCData(oldp+189,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_opcode),7);
        tracep->fullCData(oldp+190,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s_imm),7);
        tracep->fullCData(oldp+191,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s_imm_s),5);
        tracep->fullQData(oldp+192,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_op1),64);
        tracep->fullQData(oldp+194,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_op2),64);
        tracep->fullSData(oldp+196,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_I_imm),12);
        tracep->fullCData(oldp+197,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s1),3);
        tracep->fullQData(oldp+198,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_data),64);
        tracep->fullBit(oldp+200,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_w_ena));
        tracep->fullQData(oldp+201,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_data),64);
        tracep->fullBit(oldp+203,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_read));
        tracep->fullBit(oldp+204,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_write));
        tracep->fullSData(oldp+205,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr),12);
        tracep->fullBit(oldp+206,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_skip));
        tracep->fullQData(oldp+207,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_read_data),64);
        tracep->fullBit(oldp+209,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_skip));
        tracep->fullBit(oldp+210,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_open));
        tracep->fullCData(oldp+211,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_rd),5);
        tracep->fullBit(oldp+212,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_wb_en));
        tracep->fullQData(oldp+213,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_pc),64);
        tracep->fullIData(oldp+215,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_inst),32);
        tracep->fullBit(oldp+216,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_w_ena));
        tracep->fullCData(oldp+217,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd),5);
        tracep->fullQData(oldp+218,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_data),64);
        tracep->fullBit(oldp+220,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_read));
        tracep->fullQData(oldp+221,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_read_data),64);
        tracep->fullSData(oldp+223,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr),12);
        tracep->fullBit(oldp+224,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_write));
        tracep->fullBit(oldp+225,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_read));
        tracep->fullQData(oldp+226,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_data),64);
        tracep->fullCData(oldp+228,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_opcode),7);
        tracep->fullBit(oldp+229,((1U & (((0x23U == 
                                           (0x7fU & vlTOPp->SimTop__DOT__if_inst))
                                           ? 1U : 0U)
                                          ? (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                              == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2))
                                              ? ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena)
                                                  ? 0U
                                                  : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))
                                              : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))
                                          : (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                              == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2))
                                              ? ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena)
                                                  ? (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2)
                                                  : 0U)
                                              : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))))));
        tracep->fullBit(oldp+230,(((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_open) 
                                   | (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_close))));
        tracep->fullQData(oldp+231,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[0]),64);
        tracep->fullQData(oldp+233,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[1]),64);
        tracep->fullQData(oldp+235,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[2]),64);
        tracep->fullQData(oldp+237,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[3]),64);
        tracep->fullQData(oldp+239,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[4]),64);
        tracep->fullQData(oldp+241,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[5]),64);
        tracep->fullQData(oldp+243,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[6]),64);
        tracep->fullQData(oldp+245,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[7]),64);
        tracep->fullQData(oldp+247,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[8]),64);
        tracep->fullQData(oldp+249,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[9]),64);
        tracep->fullQData(oldp+251,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[10]),64);
        tracep->fullQData(oldp+253,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[11]),64);
        tracep->fullQData(oldp+255,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[12]),64);
        tracep->fullQData(oldp+257,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[13]),64);
        tracep->fullQData(oldp+259,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[14]),64);
        tracep->fullQData(oldp+261,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[15]),64);
        tracep->fullQData(oldp+263,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[16]),64);
        tracep->fullQData(oldp+265,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[17]),64);
        tracep->fullQData(oldp+267,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[18]),64);
        tracep->fullQData(oldp+269,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[19]),64);
        tracep->fullQData(oldp+271,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[20]),64);
        tracep->fullQData(oldp+273,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[21]),64);
        tracep->fullQData(oldp+275,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[22]),64);
        tracep->fullQData(oldp+277,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[23]),64);
        tracep->fullQData(oldp+279,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[24]),64);
        tracep->fullQData(oldp+281,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[25]),64);
        tracep->fullQData(oldp+283,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[26]),64);
        tracep->fullQData(oldp+285,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[27]),64);
        tracep->fullQData(oldp+287,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[28]),64);
        tracep->fullQData(oldp+289,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[29]),64);
        tracep->fullQData(oldp+291,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[30]),64);
        tracep->fullQData(oldp+293,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o[31]),64);
        tracep->fullQData(oldp+295,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus),64);
        tracep->fullQData(oldp+297,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc),64);
        tracep->fullQData(oldp+299,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mtvec),64);
        tracep->fullQData(oldp+301,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause),64);
        tracep->fullQData(oldp+303,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mip),64);
        tracep->fullQData(oldp+305,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mie),64);
        tracep->fullQData(oldp+307,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__rmstatus),64);
        tracep->fullQData(oldp+309,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcycle),64);
        tracep->fullQData(oldp+311,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mscratch),64);
        tracep->fullQData(oldp+313,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__sstatus),64);
        tracep->fullBit(oldp+315,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_skip));
        tracep->fullBit(oldp+316,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_skip));
        tracep->fullBit(oldp+317,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_skip));
        tracep->fullQData(oldp+318,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mhartid),64);
        tracep->fullQData(oldp+320,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_pc_add),64);
        tracep->fullBit(oldp+322,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_pc_write));
        tracep->fullBit(oldp+323,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_fetched));
        tracep->fullBit(oldp+324,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_fetched));
        tracep->fullBit(oldp+325,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_fetched));
        tracep->fullQData(oldp+326,((vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_op1 
                                     + ((0xfffffffffffff000ULL 
                                         & ((- (QData)((IData)(
                                                               (1U 
                                                                & ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_I_imm) 
                                                                   >> 0xbU))))) 
                                            << 0xcU)) 
                                        | (QData)((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_I_imm))))),64);
        tracep->fullQData(oldp+328,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__rdata),64);
        tracep->fullQData(oldp+330,(((2U == (IData)(vlTOPp->SimTop__DOT__axi_r_id_o))
                                      ? vlTOPp->SimTop__DOT__axi_data_read
                                      : 0ULL)),64);
        tracep->fullBit(oldp+332,(((3U == (0x7fU & vlTOPp->SimTop__DOT__if_inst))
                                    ? 1U : 0U)));
        tracep->fullBit(oldp+333,(((1U == (IData)(vlTOPp->SimTop__DOT__axi_r_id_o))
                                    ? 1U : 0U)));
        tracep->fullBit(oldp+334,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_write));
        tracep->fullBit(oldp+335,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_close));
        tracep->fullBit(oldp+336,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_mem_read));
        tracep->fullBit(oldp+337,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_mem_read));
        tracep->fullBit(oldp+338,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_mem_read));
        tracep->fullBit(oldp+339,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_mem_read));
        tracep->fullBit(oldp+340,((1U & (((0x23U == 
                                           (0x7fU & vlTOPp->SimTop__DOT__if_inst))
                                           ? 1U : 0U)
                                          ? (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                              == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1))
                                              ? ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena)
                                                  ? 0U
                                                  : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))
                                              : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))
                                          : (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                              == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1))
                                              ? ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena)
                                                  ? (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1)
                                                  : 0U)
                                              : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))))));
        tracep->fullCData(oldp+341,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__s3),3);
        tracep->fullBit(oldp+342,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_write_ready));
        tracep->fullBit(oldp+343,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_write_ready));
        tracep->fullBit(oldp+344,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena));
        tracep->fullBit(oldp+345,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_w_ena));
        tracep->fullBit(oldp+346,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ld));
        tracep->fullBit(oldp+347,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_ready1));
        tracep->fullBit(oldp+348,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_ready2));
        tracep->fullQData(oldp+349,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc_exe),64);
        tracep->fullBit(oldp+351,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt));
        tracep->fullBit(oldp+352,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__csr));
        tracep->fullBit(oldp+353,((((0x73U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_opcode)) 
                                    & (0U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr)))
                                    ? 0U : 1U)));
        tracep->fullQData(oldp+354,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[0]),64);
        tracep->fullQData(oldp+356,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[1]),64);
        tracep->fullQData(oldp+358,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[2]),64);
        tracep->fullQData(oldp+360,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[3]),64);
        tracep->fullQData(oldp+362,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[4]),64);
        tracep->fullQData(oldp+364,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[5]),64);
        tracep->fullQData(oldp+366,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[6]),64);
        tracep->fullQData(oldp+368,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[7]),64);
        tracep->fullQData(oldp+370,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[8]),64);
        tracep->fullQData(oldp+372,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[9]),64);
        tracep->fullQData(oldp+374,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[10]),64);
        tracep->fullQData(oldp+376,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[11]),64);
        tracep->fullQData(oldp+378,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[12]),64);
        tracep->fullQData(oldp+380,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[13]),64);
        tracep->fullQData(oldp+382,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[14]),64);
        tracep->fullQData(oldp+384,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[15]),64);
        tracep->fullQData(oldp+386,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[16]),64);
        tracep->fullQData(oldp+388,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[17]),64);
        tracep->fullQData(oldp+390,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[18]),64);
        tracep->fullQData(oldp+392,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[19]),64);
        tracep->fullQData(oldp+394,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[20]),64);
        tracep->fullQData(oldp+396,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[21]),64);
        tracep->fullQData(oldp+398,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[22]),64);
        tracep->fullQData(oldp+400,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[23]),64);
        tracep->fullQData(oldp+402,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[24]),64);
        tracep->fullQData(oldp+404,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[25]),64);
        tracep->fullQData(oldp+406,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[26]),64);
        tracep->fullQData(oldp+408,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[27]),64);
        tracep->fullQData(oldp+410,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[28]),64);
        tracep->fullQData(oldp+412,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[29]),64);
        tracep->fullQData(oldp+414,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[30]),64);
        tracep->fullQData(oldp+416,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o[31]),64);
        tracep->fullBit(oldp+418,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__mem_read_open));
        tracep->fullQData(oldp+419,((vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_op1 
                                     + ((0xfffffffffffff000ULL 
                                         & ((- (QData)((IData)(
                                                               (1U 
                                                                & ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_I_imm) 
                                                                   >> 0xbU))))) 
                                            << 0xcU)) 
                                        | (QData)((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_I_imm))))),64);
        tracep->fullSData(oldp+421,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__s_s),12);
        tracep->fullCData(oldp+422,((7U & (IData)(vlTOPp->SimTop__DOT__axi_write_addr))),3);
        tracep->fullQData(oldp+423,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[0]),64);
        tracep->fullQData(oldp+425,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[1]),64);
        tracep->fullQData(oldp+427,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[2]),64);
        tracep->fullQData(oldp+429,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[3]),64);
        tracep->fullQData(oldp+431,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[4]),64);
        tracep->fullQData(oldp+433,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[5]),64);
        tracep->fullQData(oldp+435,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[6]),64);
        tracep->fullQData(oldp+437,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[7]),64);
        tracep->fullQData(oldp+439,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[8]),64);
        tracep->fullQData(oldp+441,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[9]),64);
        tracep->fullQData(oldp+443,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[10]),64);
        tracep->fullQData(oldp+445,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[11]),64);
        tracep->fullQData(oldp+447,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[12]),64);
        tracep->fullQData(oldp+449,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[13]),64);
        tracep->fullQData(oldp+451,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[14]),64);
        tracep->fullQData(oldp+453,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[15]),64);
        tracep->fullQData(oldp+455,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[16]),64);
        tracep->fullQData(oldp+457,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[17]),64);
        tracep->fullQData(oldp+459,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[18]),64);
        tracep->fullQData(oldp+461,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[19]),64);
        tracep->fullQData(oldp+463,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[20]),64);
        tracep->fullQData(oldp+465,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[21]),64);
        tracep->fullQData(oldp+467,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[22]),64);
        tracep->fullQData(oldp+469,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[23]),64);
        tracep->fullQData(oldp+471,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[24]),64);
        tracep->fullQData(oldp+473,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[25]),64);
        tracep->fullQData(oldp+475,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[26]),64);
        tracep->fullQData(oldp+477,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[27]),64);
        tracep->fullQData(oldp+479,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[28]),64);
        tracep->fullQData(oldp+481,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[29]),64);
        tracep->fullQData(oldp+483,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[30]),64);
        tracep->fullQData(oldp+485,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o[31]),64);
        tracep->fullQData(oldp+487,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__mtimecmp),64);
        tracep->fullQData(oldp+489,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__mtime),64);
        tracep->fullBit(oldp+491,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__w_ena));
        tracep->fullCData(oldp+492,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__w_rd),5);
        tracep->fullBit(oldp+493,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__interrupt_ready1));
        tracep->fullBit(oldp+494,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__wb_stage));
        tracep->fullQData(oldp+495,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mepc_exe),64);
        tracep->fullBit(oldp+497,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_mie));
        tracep->fullBit(oldp+498,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_mpie));
        tracep->fullCData(oldp+499,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_fs),2);
        tracep->fullQData(oldp+500,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[0]),64);
        tracep->fullQData(oldp+502,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[1]),64);
        tracep->fullQData(oldp+504,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[2]),64);
        tracep->fullQData(oldp+506,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[3]),64);
        tracep->fullQData(oldp+508,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[4]),64);
        tracep->fullQData(oldp+510,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[5]),64);
        tracep->fullQData(oldp+512,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[6]),64);
        tracep->fullQData(oldp+514,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[7]),64);
        tracep->fullQData(oldp+516,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[8]),64);
        tracep->fullQData(oldp+518,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[9]),64);
        tracep->fullQData(oldp+520,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[10]),64);
        tracep->fullQData(oldp+522,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[11]),64);
        tracep->fullQData(oldp+524,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[12]),64);
        tracep->fullQData(oldp+526,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[13]),64);
        tracep->fullQData(oldp+528,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[14]),64);
        tracep->fullQData(oldp+530,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[15]),64);
        tracep->fullQData(oldp+532,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[16]),64);
        tracep->fullQData(oldp+534,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[17]),64);
        tracep->fullQData(oldp+536,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[18]),64);
        tracep->fullQData(oldp+538,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[19]),64);
        tracep->fullQData(oldp+540,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[20]),64);
        tracep->fullQData(oldp+542,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[21]),64);
        tracep->fullQData(oldp+544,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[22]),64);
        tracep->fullQData(oldp+546,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[23]),64);
        tracep->fullQData(oldp+548,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[24]),64);
        tracep->fullQData(oldp+550,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[25]),64);
        tracep->fullQData(oldp+552,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[26]),64);
        tracep->fullQData(oldp+554,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[27]),64);
        tracep->fullQData(oldp+556,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[28]),64);
        tracep->fullQData(oldp+558,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[29]),64);
        tracep->fullQData(oldp+560,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[30]),64);
        tracep->fullQData(oldp+562,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o[31]),64);
        tracep->fullQData(oldp+564,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__w_data),64);
        tracep->fullQData(oldp+566,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[0]),64);
        tracep->fullQData(oldp+568,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[1]),64);
        tracep->fullQData(oldp+570,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[2]),64);
        tracep->fullQData(oldp+572,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[3]),64);
        tracep->fullQData(oldp+574,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[4]),64);
        tracep->fullQData(oldp+576,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[5]),64);
        tracep->fullQData(oldp+578,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[6]),64);
        tracep->fullQData(oldp+580,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[7]),64);
        tracep->fullQData(oldp+582,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[8]),64);
        tracep->fullQData(oldp+584,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[9]),64);
        tracep->fullQData(oldp+586,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[10]),64);
        tracep->fullQData(oldp+588,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[11]),64);
        tracep->fullQData(oldp+590,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[12]),64);
        tracep->fullQData(oldp+592,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[13]),64);
        tracep->fullQData(oldp+594,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[14]),64);
        tracep->fullQData(oldp+596,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[15]),64);
        tracep->fullQData(oldp+598,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[16]),64);
        tracep->fullQData(oldp+600,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[17]),64);
        tracep->fullQData(oldp+602,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[18]),64);
        tracep->fullQData(oldp+604,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[19]),64);
        tracep->fullQData(oldp+606,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[20]),64);
        tracep->fullQData(oldp+608,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[21]),64);
        tracep->fullQData(oldp+610,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[22]),64);
        tracep->fullQData(oldp+612,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[23]),64);
        tracep->fullQData(oldp+614,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[24]),64);
        tracep->fullQData(oldp+616,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[25]),64);
        tracep->fullQData(oldp+618,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[26]),64);
        tracep->fullQData(oldp+620,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[27]),64);
        tracep->fullQData(oldp+622,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[28]),64);
        tracep->fullQData(oldp+624,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[29]),64);
        tracep->fullQData(oldp+626,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[30]),64);
        tracep->fullQData(oldp+628,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs[31]),64);
        tracep->fullBit(oldp+630,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wen));
        tracep->fullCData(oldp+631,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wdest),8);
        tracep->fullQData(oldp+632,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wdata),64);
        tracep->fullQData(oldp+634,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_pc),64);
        tracep->fullIData(oldp+636,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_inst),32);
        tracep->fullBit(oldp+637,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_valid));
        tracep->fullBit(oldp+638,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__trap));
        tracep->fullCData(oldp+639,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__trap_code),8);
        tracep->fullQData(oldp+640,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cycleCnt),64);
        tracep->fullQData(oldp+642,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__instrCnt),64);
        tracep->fullBit(oldp+644,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__skip));
        tracep->fullQData(oldp+645,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[0]),64);
        tracep->fullQData(oldp+647,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[1]),64);
        tracep->fullQData(oldp+649,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[2]),64);
        tracep->fullQData(oldp+651,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[3]),64);
        tracep->fullQData(oldp+653,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[4]),64);
        tracep->fullQData(oldp+655,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[5]),64);
        tracep->fullQData(oldp+657,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[6]),64);
        tracep->fullQData(oldp+659,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[7]),64);
        tracep->fullQData(oldp+661,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[8]),64);
        tracep->fullQData(oldp+663,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[9]),64);
        tracep->fullQData(oldp+665,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[10]),64);
        tracep->fullQData(oldp+667,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[11]),64);
        tracep->fullQData(oldp+669,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[12]),64);
        tracep->fullQData(oldp+671,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[13]),64);
        tracep->fullQData(oldp+673,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[14]),64);
        tracep->fullQData(oldp+675,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[15]),64);
        tracep->fullQData(oldp+677,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[16]),64);
        tracep->fullQData(oldp+679,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[17]),64);
        tracep->fullQData(oldp+681,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[18]),64);
        tracep->fullQData(oldp+683,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[19]),64);
        tracep->fullQData(oldp+685,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[20]),64);
        tracep->fullQData(oldp+687,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[21]),64);
        tracep->fullQData(oldp+689,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[22]),64);
        tracep->fullQData(oldp+691,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[23]),64);
        tracep->fullQData(oldp+693,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[24]),64);
        tracep->fullQData(oldp+695,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[25]),64);
        tracep->fullQData(oldp+697,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[26]),64);
        tracep->fullQData(oldp+699,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[27]),64);
        tracep->fullQData(oldp+701,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[28]),64);
        tracep->fullQData(oldp+703,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[29]),64);
        tracep->fullQData(oldp+705,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[30]),64);
        tracep->fullQData(oldp+707,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff[31]),64);
        tracep->fullIData(oldp+709,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__intrNO),32);
        tracep->fullIData(oldp+710,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__cause),32);
        tracep->fullQData(oldp+711,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mtvec_diff),64);
        tracep->fullQData(oldp+713,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_diff),64);
        tracep->fullQData(oldp+715,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__sstatus_diff),64);
        tracep->fullQData(oldp+717,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc_diff),64);
        tracep->fullQData(oldp+719,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_diff),64);
        tracep->fullQData(oldp+721,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mip_diff),64);
        tracep->fullQData(oldp+723,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mie_diff),64);
        tracep->fullQData(oldp+725,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mscratch_diff),64);
        tracep->fullQData(oldp+727,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mhartid_diff),64);
        tracep->fullQData(oldp+729,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__rmstatus_diff),64);
        tracep->fullBit(oldp+731,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_mie));
        tracep->fullBit(oldp+732,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_mpie));
        tracep->fullCData(oldp+733,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_fs),2);
        tracep->fullQData(oldp+734,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0U]),64);
        tracep->fullQData(oldp+736,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [1U]),64);
        tracep->fullQData(oldp+738,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [2U]),64);
        tracep->fullQData(oldp+740,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [3U]),64);
        tracep->fullQData(oldp+742,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [4U]),64);
        tracep->fullQData(oldp+744,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [5U]),64);
        tracep->fullQData(oldp+746,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [6U]),64);
        tracep->fullQData(oldp+748,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [7U]),64);
        tracep->fullQData(oldp+750,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [8U]),64);
        tracep->fullQData(oldp+752,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [9U]),64);
        tracep->fullQData(oldp+754,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xaU]),64);
        tracep->fullQData(oldp+756,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xbU]),64);
        tracep->fullQData(oldp+758,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xcU]),64);
        tracep->fullQData(oldp+760,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xdU]),64);
        tracep->fullQData(oldp+762,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xeU]),64);
        tracep->fullQData(oldp+764,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0xfU]),64);
        tracep->fullQData(oldp+766,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x10U]),64);
        tracep->fullQData(oldp+768,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x11U]),64);
        tracep->fullQData(oldp+770,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x12U]),64);
        tracep->fullQData(oldp+772,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x13U]),64);
        tracep->fullQData(oldp+774,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x14U]),64);
        tracep->fullQData(oldp+776,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x15U]),64);
        tracep->fullQData(oldp+778,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x16U]),64);
        tracep->fullQData(oldp+780,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x17U]),64);
        tracep->fullQData(oldp+782,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x18U]),64);
        tracep->fullQData(oldp+784,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x19U]),64);
        tracep->fullQData(oldp+786,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1aU]),64);
        tracep->fullQData(oldp+788,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1bU]),64);
        tracep->fullQData(oldp+790,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1cU]),64);
        tracep->fullQData(oldp+792,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1dU]),64);
        tracep->fullQData(oldp+794,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1eU]),64);
        tracep->fullQData(oldp+796,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff
                                    [0x1fU]),64);
        tracep->fullCData(oldp+798,((7U & (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__trap_code))),3);
        tracep->fullBit(oldp+799,(vlTOPp->clock));
        tracep->fullBit(oldp+800,(vlTOPp->reset));
        tracep->fullQData(oldp+801,(vlTOPp->io_logCtrl_log_begin),64);
        tracep->fullQData(oldp+803,(vlTOPp->io_logCtrl_log_end),64);
        tracep->fullQData(oldp+805,(vlTOPp->io_logCtrl_log_level),64);
        tracep->fullBit(oldp+807,(vlTOPp->io_perfInfo_clean));
        tracep->fullBit(oldp+808,(vlTOPp->io_perfInfo_dump));
        tracep->fullBit(oldp+809,(vlTOPp->io_uart_out_valid));
        tracep->fullCData(oldp+810,(vlTOPp->io_uart_out_ch),8);
        tracep->fullBit(oldp+811,(vlTOPp->io_uart_in_valid));
        tracep->fullCData(oldp+812,(vlTOPp->io_uart_in_ch),8);
        tracep->fullBit(oldp+813,(vlTOPp->io_memAXI_0_aw_ready));
        tracep->fullBit(oldp+814,(vlTOPp->io_memAXI_0_aw_valid));
        tracep->fullQData(oldp+815,(vlTOPp->io_memAXI_0_aw_bits_addr),64);
        tracep->fullCData(oldp+817,(vlTOPp->io_memAXI_0_aw_bits_prot),3);
        tracep->fullCData(oldp+818,(vlTOPp->io_memAXI_0_aw_bits_id),4);
        tracep->fullBit(oldp+819,(vlTOPp->io_memAXI_0_aw_bits_user));
        tracep->fullCData(oldp+820,(vlTOPp->io_memAXI_0_aw_bits_len),8);
        tracep->fullCData(oldp+821,(vlTOPp->io_memAXI_0_aw_bits_size),3);
        tracep->fullCData(oldp+822,(vlTOPp->io_memAXI_0_aw_bits_burst),2);
        tracep->fullBit(oldp+823,(vlTOPp->io_memAXI_0_aw_bits_lock));
        tracep->fullCData(oldp+824,(vlTOPp->io_memAXI_0_aw_bits_cache),4);
        tracep->fullCData(oldp+825,(vlTOPp->io_memAXI_0_aw_bits_qos),4);
        tracep->fullBit(oldp+826,(vlTOPp->io_memAXI_0_w_ready));
        tracep->fullBit(oldp+827,(vlTOPp->io_memAXI_0_w_valid));
        tracep->fullQData(oldp+828,(vlTOPp->io_memAXI_0_w_bits_data[0]),64);
        tracep->fullQData(oldp+830,(vlTOPp->io_memAXI_0_w_bits_data[1]),64);
        tracep->fullQData(oldp+832,(vlTOPp->io_memAXI_0_w_bits_data[2]),64);
        tracep->fullQData(oldp+834,(vlTOPp->io_memAXI_0_w_bits_data[3]),64);
        tracep->fullCData(oldp+836,(vlTOPp->io_memAXI_0_w_bits_strb),8);
        tracep->fullBit(oldp+837,(vlTOPp->io_memAXI_0_w_bits_last));
        tracep->fullBit(oldp+838,(vlTOPp->io_memAXI_0_b_ready));
        tracep->fullBit(oldp+839,(vlTOPp->io_memAXI_0_b_valid));
        tracep->fullCData(oldp+840,(vlTOPp->io_memAXI_0_b_bits_resp),2);
        tracep->fullCData(oldp+841,(vlTOPp->io_memAXI_0_b_bits_id),4);
        tracep->fullBit(oldp+842,(vlTOPp->io_memAXI_0_b_bits_user));
        tracep->fullBit(oldp+843,(vlTOPp->io_memAXI_0_ar_ready));
        tracep->fullBit(oldp+844,(vlTOPp->io_memAXI_0_ar_valid));
        tracep->fullQData(oldp+845,(vlTOPp->io_memAXI_0_ar_bits_addr),64);
        tracep->fullCData(oldp+847,(vlTOPp->io_memAXI_0_ar_bits_prot),3);
        tracep->fullCData(oldp+848,(vlTOPp->io_memAXI_0_ar_bits_id),4);
        tracep->fullBit(oldp+849,(vlTOPp->io_memAXI_0_ar_bits_user));
        tracep->fullCData(oldp+850,(vlTOPp->io_memAXI_0_ar_bits_len),8);
        tracep->fullCData(oldp+851,(vlTOPp->io_memAXI_0_ar_bits_size),3);
        tracep->fullCData(oldp+852,(vlTOPp->io_memAXI_0_ar_bits_burst),2);
        tracep->fullBit(oldp+853,(vlTOPp->io_memAXI_0_ar_bits_lock));
        tracep->fullCData(oldp+854,(vlTOPp->io_memAXI_0_ar_bits_cache),4);
        tracep->fullCData(oldp+855,(vlTOPp->io_memAXI_0_ar_bits_qos),4);
        tracep->fullBit(oldp+856,(vlTOPp->io_memAXI_0_r_ready));
        tracep->fullBit(oldp+857,(vlTOPp->io_memAXI_0_r_valid));
        tracep->fullCData(oldp+858,(vlTOPp->io_memAXI_0_r_bits_resp),2);
        tracep->fullQData(oldp+859,(vlTOPp->io_memAXI_0_r_bits_data[0]),64);
        tracep->fullQData(oldp+861,(vlTOPp->io_memAXI_0_r_bits_data[1]),64);
        tracep->fullQData(oldp+863,(vlTOPp->io_memAXI_0_r_bits_data[2]),64);
        tracep->fullQData(oldp+865,(vlTOPp->io_memAXI_0_r_bits_data[3]),64);
        tracep->fullBit(oldp+867,(vlTOPp->io_memAXI_0_r_bits_last));
        tracep->fullCData(oldp+868,(vlTOPp->io_memAXI_0_r_bits_id),4);
        tracep->fullBit(oldp+869,(vlTOPp->io_memAXI_0_r_bits_user));
        tracep->fullCData(oldp+870,(((IData)(vlTOPp->reset)
                                      ? 0U : ((1U & 
                                               (((3U 
                                                  == 
                                                  (0x7fU 
                                                   & vlTOPp->SimTop__DOT__if_inst))
                                                  ? 1U
                                                  : 0U) 
                                                & (~ 
                                                   ((1U 
                                                     == (IData)(vlTOPp->SimTop__DOT__axi_r_id_o))
                                                     ? 1U
                                                     : 0U))))
                                               ? 1U
                                               : 2U))),4);
        tracep->fullQData(oldp+871,(vlTOPp->io_memAXI_0_r_bits_data
                                    [0U]),64);
        tracep->fullQData(oldp+873,(((0x2004000ULL 
                                      == (0xfffffffffffffff8ULL 
                                          & vlTOPp->SimTop__DOT__axi_write_addr))
                                      ? vlTOPp->SimTop__DOT__w_data
                                      : (((0x2004000ULL 
                                           == (0xfffffffffffffff8ULL 
                                               & vlTOPp->SimTop__DOT__axi_read_addr)) 
                                          & ((1U == (IData)(vlTOPp->io_memAXI_0_r_bits_id)) 
                                             & (IData)(vlTOPp->SimTop__DOT__r_hs)))
                                          ? vlTOPp->io_memAXI_0_r_bits_data
                                         [0U] : 0ULL))),64);
        tracep->fullQData(oldp+875,(((0x200bff8ULL 
                                      == (0xfffffffffffffff8ULL 
                                          & vlTOPp->SimTop__DOT__axi_write_addr))
                                      ? vlTOPp->SimTop__DOT__w_data
                                      : (((0x200bff8ULL 
                                           == (0xfffffffffffffff8ULL 
                                               & vlTOPp->SimTop__DOT__axi_read_addr)) 
                                          & ((1U == (IData)(vlTOPp->io_memAXI_0_r_bits_id)) 
                                             & (IData)(vlTOPp->SimTop__DOT__r_hs)))
                                          ? vlTOPp->io_memAXI_0_r_bits_data
                                         [0U] : 0ULL))),64);
        tracep->fullBit(oldp+877,((((IData)(vlTOPp->reset) 
                                    | ((IData)(vlTOPp->SimTop__DOT__mem_write) 
                                       & (0U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state)))) 
                                   | (0U == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state)))));
        tracep->fullCData(oldp+878,(((IData)(vlTOPp->SimTop__DOT__mem_write)
                                      ? (IData)(vlTOPp->io_memAXI_0_b_bits_resp)
                                      : (IData)(vlTOPp->io_memAXI_0_r_bits_resp))),2);
        tracep->fullQData(oldp+879,(((vlTOPp->io_memAXI_0_r_bits_data
                                      [0U] & (((QData)((IData)(
                                                               vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[3U])) 
                                               << 0x20U) 
                                              | (QData)((IData)(
                                                                vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask[2U])))) 
                                     << (0x3fU & ((IData)(0x3fU) 
                                                  - 
                                                  (0x38U 
                                                   & ((IData)(vlTOPp->SimTop__DOT__axi_read_addr) 
                                                      << 3U)))))),64);
        tracep->fullQData(oldp+881,(((IData)(vlTOPp->reset)
                                      ? 0ULL : ((1U 
                                                 & (((0x23U 
                                                      == 
                                                      (0x7fU 
                                                       & vlTOPp->SimTop__DOT__if_inst))
                                                      ? 1U
                                                      : 0U)
                                                     ? 
                                                    (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1))
                                                      ? 
                                                     ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena)
                                                       ? 0U
                                                       : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))
                                                      : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))
                                                     : 
                                                    (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1))
                                                      ? 
                                                     ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena)
                                                       ? (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1)
                                                       : 0U)
                                                      : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1))))
                                                 ? 
                                                vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs
                                                [vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1]
                                                 : 
                                                ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ld)
                                                  ? 
                                                 vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs
                                                 [vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1]
                                                  : 0ULL)))),64);
        tracep->fullQData(oldp+883,(((IData)(vlTOPp->reset)
                                      ? 0ULL : ((1U 
                                                 & (((0x23U 
                                                      == 
                                                      (0x7fU 
                                                       & vlTOPp->SimTop__DOT__if_inst))
                                                      ? 1U
                                                      : 0U)
                                                     ? 
                                                    (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2))
                                                      ? 
                                                     ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena)
                                                       ? 0U
                                                       : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))
                                                      : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))
                                                     : 
                                                    (((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd) 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2))
                                                      ? 
                                                     ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena)
                                                       ? (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2)
                                                       : 0U)
                                                      : (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2))))
                                                 ? 
                                                vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs
                                                [vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2]
                                                 : 
                                                ((IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ld)
                                                  ? 
                                                 vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs
                                                 [vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2]
                                                  : 0ULL)))),64);
        tracep->fullQData(oldp+885,(((IData)(vlTOPp->reset)
                                      ? 0ULL : (((0x73U 
                                                  == 
                                                  (0x7fU 
                                                   & vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst))
                                                  ? 1U
                                                  : 0U)
                                                 ? 
                                                (((((((((0U 
                                                         == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr)) 
                                                        | (0x300U 
                                                           == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                       | (0x341U 
                                                          == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                      | (0x305U 
                                                         == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                     | (0x342U 
                                                        == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                    | (0x344U 
                                                       == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                   | (0x304U 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))) 
                                                  | (0xf14U 
                                                     == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr)))
                                                  ? 
                                                 ((0U 
                                                   == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                   ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc
                                                   : 
                                                  ((0x300U 
                                                    == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                    ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus
                                                    : 
                                                   ((0x341U 
                                                     == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                     ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc
                                                     : 
                                                    ((0x305U 
                                                      == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                      ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mtvec
                                                      : 
                                                     ((0x342U 
                                                       == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                       ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause
                                                       : 
                                                      ((0x344U 
                                                        == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                        ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mip
                                                        : 
                                                       ((0x304U 
                                                         == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                         ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mie
                                                         : vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mhartid)))))))
                                                  : 
                                                 ((0x340U 
                                                   == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                   ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mscratch
                                                   : 
                                                  ((0xb00U 
                                                    == (IData)(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr))
                                                    ? vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcycle
                                                    : 0ULL)))
                                                 : 0ULL))),64);
        tracep->fullBit(oldp+887,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__inst_valid));
        tracep->fullCData(oldp+888,(vlTOPp->SimTop__DOT__aw_prot),3);
        tracep->fullCData(oldp+889,(3U),4);
        tracep->fullBit(oldp+890,(vlTOPp->SimTop__DOT__aw_user));
        tracep->fullCData(oldp+891,(3U),3);
        tracep->fullCData(oldp+892,(1U),2);
        tracep->fullBit(oldp+893,(vlTOPp->SimTop__DOT__aw_lock));
        tracep->fullCData(oldp+894,(vlTOPp->SimTop__DOT__aw_cache),4);
        tracep->fullCData(oldp+895,(vlTOPp->SimTop__DOT__aw_qos),4);
        tracep->fullCData(oldp+896,(vlTOPp->SimTop__DOT__aw_region),4);
        tracep->fullBit(oldp+897,(1U));
        tracep->fullBit(oldp+898,(vlTOPp->SimTop__DOT__w_user));
        tracep->fullCData(oldp+899,(vlTOPp->SimTop__DOT__ar_prot),3);
        tracep->fullBit(oldp+900,(vlTOPp->SimTop__DOT__ar_user));
        tracep->fullBit(oldp+901,(vlTOPp->SimTop__DOT__ar_lock));
        tracep->fullCData(oldp+902,(vlTOPp->SimTop__DOT__ar_cache),4);
        tracep->fullCData(oldp+903,(vlTOPp->SimTop__DOT__ar_qos),4);
        tracep->fullCData(oldp+904,(vlTOPp->SimTop__DOT__ar_region),4);
        tracep->fullBit(oldp+905,(0U));
        tracep->fullBit(oldp+906,(vlTOPp->SimTop__DOT__axi_write_ready));
        tracep->fullIData(oldp+907,(0x40U),32);
        tracep->fullIData(oldp+908,(4U),32);
        tracep->fullIData(oldp+909,(1U),32);
        tracep->fullCData(oldp+910,(0U),2);
        tracep->fullCData(oldp+911,(2U),2);
        tracep->fullCData(oldp+912,(3U),2);
        tracep->fullIData(oldp+913,(3U),32);
        tracep->fullIData(oldp+914,(6U),32);
        tracep->fullIData(oldp+915,(0x80U),32);
        tracep->fullBit(oldp+916,(0U));
        tracep->fullBit(oldp+917,(vlTOPp->SimTop__DOT__ysyx_210448_u_axi_rw__DOT__clint_skip_ready));
        tracep->fullQData(oldp+918,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_pc_if),64);
        tracep->fullIData(oldp+920,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_inst_if),32);
        tracep->fullBit(oldp+921,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_clk));
        tracep->fullBit(oldp+922,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_open));
        tracep->fullBit(oldp+923,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_open));
        tracep->fullQData(oldp+924,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_pc_id),64);
        tracep->fullIData(oldp+926,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst_id),32);
        tracep->fullCData(oldp+927,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_opcode_id),7);
        tracep->fullBit(oldp+928,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_ok));
        tracep->fullBit(oldp+929,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_skip));
        tracep->fullQData(oldp+930,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__t),64);
        tracep->fullQData(oldp+932,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_data),64);
        tracep->fullBit(oldp+934,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__c_interrupt));
        tracep->fullCData(oldp+935,(2U),4);
        tracep->fullCData(oldp+936,(1U),4);
        tracep->fullBit(oldp+937,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_axi_stop));
        tracep->fullBit(oldp+938,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_mem_read));
        tracep->fullBit(oldp+939,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__l_double));
        tracep->fullBit(oldp+940,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__close));
        tracep->fullBit(oldp+941,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_mem_write));
        tracep->fullBit(oldp+942,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__if_mem_write));
        tracep->fullBit(oldp+943,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__id_mem_write));
        tracep->fullQData(oldp+944,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_arch),64);
        tracep->fullQData(oldp+946,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_diff_diff),64);
        tracep->fullQData(oldp+948,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__mret),64);
        tracep->fullBit(oldp+950,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_mie));
        tracep->fullQData(oldp+951,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_if_stage__DOT__addr),64);
        tracep->fullSData(oldp+953,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__s_s),12);
        tracep->fullQData(oldp+954,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__mepc_reserve),64);
        tracep->fullCData(oldp+956,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__s5),3);
        tracep->fullSData(oldp+957,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__mem_I_imm_I),12);
        tracep->fullBit(oldp+958,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_write_ready));
        tracep->fullQData(oldp+959,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_add_ready),64);
        tracep->fullBit(oldp+961,(vlTOPp->SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_jump));
        tracep->fullCData(oldp+962,(0U),8);
        tracep->fullQData(oldp+963,(0ULL),64);
    }
}
